From 9aaf3de90ca9e9139e4dfaaf8e227fc10242f1e2 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 15 Jan 2024 22:17:49 +0100 Subject: [PATCH] radeonsi: emit cache flushes before draw registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes #9807 but I don't understand why. Emitting cache flushes before VGT_PRIMITIVE_TYPE is what makes the problem go away but changing the order in si_draw() is clearer. The only cases where sctx->flags is modified in si_emit_draw_registers is handled using si_emit_cache_flush_direct so we can move cache flushing up without any addtional conditionals. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9807 Fixes: 1e4b5390425 ("radeonsi: handle deferred cache flushes as a state (si_atom)") Reviewed-by: Marek Olšák Part-of: (cherry picked from commit 0e16da89fefb8ec38fafbd26ca4a60fc3c1e3b4c) --- .pick_status.json | 2 +- src/gallium/drivers/radeonsi/si_state_draw.cpp | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 032dc4fc2f3..02a229d0360 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -674,7 +674,7 @@ "description": "radeonsi: emit cache flushes before draw registers", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "1e4b5390425c13b493b05bdaf17a94a6f2f32057", "notes": null diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 987765d8e33..9532d368690 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -882,8 +882,10 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, sctx->family == CHIP_HAWAII && G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) && num_instanced_prims_less_than(indirect, prim, min_vertex_count, instance_count, 2, sctx->patch_vertices)) { - sctx->flags |= SI_CONTEXT_VGT_FLUSH; - si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush); + /* The cache flushes should have been emitted already. */ + assert(sctx->flags == 0); + sctx->flags = SI_CONTEXT_VGT_FLUSH; + si_emit_cache_flush_direct(sctx); } } @@ -2237,12 +2239,13 @@ static void si_draw(struct pipe_context *ctx, /* Emit states. */ si_emit_rasterizer_prim_state(sctx); - /* This must be done before si_emit_all_states because it can set cache flush flags. */ + /* This emits states and flushes caches. */ + si_emit_all_states(sctx, masked_atoms); + /* This can be done after si_emit_all_states because it doesn't set cache flush flags. */ si_emit_draw_registers (sctx, indirect, prim, index_size, instance_count, primitive_restart, info->restart_index, min_direct_count); - /* This emits states and flushes caches. */ - si_emit_all_states(sctx, masked_atoms); + /* <-- CUs are idle here if the cache_flush state waited. */ /* This must be done after si_emit_all_states, which can affect this. */