OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

etnaviv: isa: Support src2 for texld

Browse Source 
We need to add a variant of the texld instruction, which is used with a shadow
samper and passed the shadow reference value via src2.

Blob generates such texld's for deqp's GLES3.functional.texture.shadow.2d.* (GC3000).
Fixes spec@arb_depth_texture@texdepth.

Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
(cherry picked from commit 5daa47c1f8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>
This commit is contained in:
Christian Gmeiner
2024-12-20 22:48:48 +01:00
committed by Dylan Baker
parent 6314df61f8
commit 9a8f411ec4
3 changed files with 30 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
.pick_status.json
View File

@@ -234,7 +234,7 @@
"description": "etnaviv: isa: Support src2 for texld",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "abe5bd35d0bcd10ff08c4dd0239ab1fbeea3db49",
"notes": null

30
src/etnaviv/isa/etnaviv.xml
View File

@@ -368,6 +368,10 @@ SPDX-License-Identifier: MIT
({SRC0_USE} != 0) &amp;&amp; ({SRC1_USE} != 0)
</expr>
<expr name="#instruction-has-src2">
({SRC2_USE} != 0)
</expr>
<bitset name="#instruction-alu-no-dst-maybe-src0-src1" extends="#instruction-alu">
<doc>Needed for texkill</doc>
<display>
@@ -695,13 +699,19 @@ SPDX-License-Identifier: MIT
<pattern pos="127">0</pattern>
</bitset>
<bitset name="#instruction-tex-src0" extends="#instruction-tex">
<bitset name="#instruction-tex-src0-maybe-src2" extends="#instruction-tex">
<meta has_dest="true" valid_srcs="0"/>
<display>
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, void
</display>
<override expr="#instruction-has-src2">
<display>
{INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, {SRC2}
</display>
</override>
<!-- SRC0 -->
<pattern pos="43">1</pattern> <!-- SRC0_USE -->
<field name="SRC0_REG" low="44" high="52" type="uint"/>
@@ -723,13 +733,15 @@ SPDX-License-Identifier: MIT
<pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP -->
<!-- SRC2 -->
<pattern pos="99">0</pattern> <!-- SRC2_USE -->
<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
<field name="SRC2_USE" pos="99" type="bool"/> <!-- SRC2_USE -->
<field name="SRC2_REG" low="100" high="108" type="uint"/>
<field name="SRC2" low="110" high="119" type="#instruction-src">
<param name="SRC2_REG" as="SRC_REG"/>
<param name="SRC2_AMODE" as="SRC_AMODE"/>
<param name="SRC2_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/>
<field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/>
</bitset>
<bitset name="#instruction-tex-src0-src1-src2" extends="#instruction-tex">
@@ -1180,7 +1192,7 @@ SPDX-License-Identifier: MIT
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="texld" extends="#instruction-tex-src0">
<bitset name="texld" extends="#instruction-tex-src0-maybe-src2">
<pattern low="0" high="5">011000</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>

8
src/etnaviv/isa/tests/disasm.cpp
View File

@@ -373,3 +373,11 @@ INSTANTIATE_TEST_SUITE_P(ConvVariants, DisasmTest,
)
);
// clang-format on
// clang-format off
INSTANTIATE_TEST_SUITE_P(ShadowSampler, DisasmTest,
testing::Values(
disasm_state{ {0x00811018, 0x15001800, 0x00000000, 0x002a8018}, "texld t1.x___, tex0.xxxx, t1.xyyy, void, t1.zzzz\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM}
)
);
// clang-format on