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radv: remove radv_graphics_pipeline::use_per_attribute_vb_descs

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Use the VS shader info instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22192>
This commit is contained in:
Samuel Pitoiset
2023-03-29 15:49:47 +02:00
committed by Marge Bot
parent 5d85966805
commit 99bca4cb50
5 changed files with 7 additions and 8 deletions
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6
src/amd/vulkan/radv_cmd_buffer.c
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@@ -4715,7 +4715,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
uint64_t va;
const struct radv_vs_input_state *vs_state =
vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
assert(!vs_state || pipeline->use_per_attribute_vb_descs);
assert(!vs_state || vs_shader->info.vs.use_per_attribute_vb_descs);
const struct ac_vtx_format_info *vtx_info_table =
vs_state ? ac_get_vtx_format_info_table(chip, family) : NULL;
@@ -4736,7 +4736,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
unsigned binding =
vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
: (pipeline->use_per_attribute_vb_descs ? pipeline->attrib_bindings[i] : i);
: (vs_shader->info.vs.use_per_attribute_vb_descs ? pipeline->attrib_bindings[i] : i);
struct radv_buffer *buffer = cmd_buffer->vertex_binding_buffers[binding];
unsigned num_records;
unsigned stride;
@@ -4805,7 +4805,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
num_records = vk_buffer_range(&buffer->vk, offset, VK_WHOLE_SIZE);
}
if (pipeline->use_per_attribute_vb_descs) {
if (vs_shader->info.vs.use_per_attribute_vb_descs) {
uint32_t attrib_end =
vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i] : pipeline->attrib_ends[i];

3
src/amd/vulkan/radv_debug.c
View File

@@ -420,6 +420,7 @@ static void
radv_dump_vertex_descriptors(const struct radv_device *device,
struct radv_graphics_pipeline *pipeline, FILE *f)
{
struct radv_shader *vs = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
void *ptr = (uint64_t *)device->trace_id_ptr;
uint32_t count = util_bitcount(pipeline->vb_desc_usage_mask);
uint32_t *vb_ptr = &((uint32_t *)ptr)[3];
@@ -428,7 +429,7 @@ radv_dump_vertex_descriptors(const struct radv_device *device,
return;
fprintf(f, "Num vertex %s: %d\n",
pipeline->use_per_attribute_vb_descs ? "attributes" : "bindings", count);
vs->info.vs.use_per_attribute_vb_descs ? "attributes" : "bindings", count);
for (uint32_t i = 0; i < count; i++) {
uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
uint64_t va = 0;

4
src/amd/vulkan/radv_device_generated_commands.c
View File

@@ -1190,11 +1190,11 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
while (mask) {
unsigned i = u_bit_scan(&mask);
unsigned binding =
graphics_pipeline->use_per_attribute_vb_descs ? graphics_pipeline->attrib_bindings[i] : i;
vertex_shader->info.vs.use_per_attribute_vb_descs ? graphics_pipeline->attrib_bindings[i] : i;
uint32_t attrib_end = graphics_pipeline->attrib_ends[i];
params.vbo_bind_mask |= ((layout->bind_vbo_mask >> binding) & 1u) << idx;
vbo_info[2 * idx] = ((graphics_pipeline->use_per_attribute_vb_descs ? 1u : 0u) << 31) |
vbo_info[2 * idx] = ((vertex_shader->info.vs.use_per_attribute_vb_descs ? 1u : 0u) << 31) |
layout->vbo_offsets[binding];
vbo_info[2 * idx + 1] = graphics_pipeline->attrib_index_offset[i] | (attrib_end << 16);
++idx;

1
src/amd/vulkan/radv_pipeline.c
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@@ -4409,7 +4409,6 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
}
}
pipeline->use_per_attribute_vb_descs = vs_info->vs.use_per_attribute_vb_descs;
pipeline->last_vertex_attrib_bit = util_last_bit(vs_info->vs.vb_desc_usage_mask);
if (pipeline->base.shaders[MESA_SHADER_VERTEX])
pipeline->next_vertex_stage = MESA_SHADER_VERTEX;

1
src/amd/vulkan/radv_private.h
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@@ -2203,7 +2203,6 @@ struct radv_graphics_pipeline {
bool uses_drawid;
bool uses_baseinstance;
bool use_per_attribute_vb_descs;
bool can_use_simple_input;
/* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel