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treewide: Use nir_trim_vector more

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Via Coccinelle patches

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, (1 << c) - 1)
    +nir_trim_vector(b, a, c)

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, BITFIELD_MASK(c))
    +nir_trim_vector(b, a, c)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 3)
    +nir_trim_vector(b, a, 2)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 7)
    +nir_trim_vector(b, a, 3)

Plus a fixup for pointless trimming an immediate in RADV and radeonsi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
This commit is contained in:
Alyssa Rosenzweig
2023-05-31 21:08:47 -04:00
committed by Marge Bot
parent 68eda9456f
commit 99a00e2247
46 changed files with 114 additions and 99 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/intel/compiler/brw_nir_lower_storage_image.c
View File

@@ -116,7 +116,7 @@ image_address(nir_builder *b, const struct intel_device_info *devinfo,
*/
nir_ssa_def *xypos = (coord->num_components == 1) ?
nir_vec2(b, coord, nir_imm_int(b, 0)) :
nir_channels(b, coord, 0x3);
nir_trim_vector(b, coord, 2);
xypos = nir_iadd(b, xypos, offset);
/* The layout of 3-D textures in memory is sort-of like a tiling
@@ -174,8 +174,8 @@ image_address(nir_builder *b, const struct intel_device_info *devinfo,
/* Calculate the minor x and y indices. */
nir_ssa_def *minor = nir_ubfe(b, xypos, nir_imm_int(b, 0),
nir_channels(b, tiling, 0x3));
nir_ssa_def *major = nir_ushr(b, xypos, nir_channels(b, tiling, 0x3));
nir_trim_vector(b, tiling, 2));
nir_ssa_def *major = nir_ushr(b, xypos, nir_trim_vector(b, tiling, 2));
/* Calculate the texel index from the start of the tile row and the
* vertical coordinate of the row.

4
src/intel/compiler/brw_nir_rt_builder.h
View File

@@ -313,7 +313,7 @@ brw_nir_rt_load_globals_addr(nir_builder *b,
{
nir_ssa_def *data;
data = brw_nir_rt_load_const(b, 16, addr, nir_imm_true(b));
defs->base_mem_addr = nir_pack_64_2x32(b, nir_channels(b, data, 0x3));
defs->base_mem_addr = nir_pack_64_2x32(b, nir_trim_vector(b, data, 2));
defs->call_stack_handler_addr =
nir_pack_64_2x32(b, nir_channels(b, data, 0x3 << 2));
@@ -781,7 +781,7 @@ brw_nir_rt_load_mem_ray_from_addr(nir_builder *b,
brw_nir_rt_load(b, nir_iadd_imm(b, ray_addr, 48), 16, 4, 32),
};
defs->orig = nir_channels(b, data[0], 0x7);
defs->orig = nir_trim_vector(b, data[0], 3);
defs->dir = nir_vec3(b, nir_channel(b, data[0], 3),
nir_channel(b, data[1], 0),
nir_channel(b, data[1], 1));