intel/compiler: Move spill/fill tracking to the register allocator
Originally, we had virtual opcodes for scratch access, and let the generator count spills/fills separately from other sends. Later, we started using the generic SHADER_OPCODE_SEND for spills/fills on some generations of hardware, and simply detected stateless messages there. But then we started using stateless messages for other things: - anv uses stateless messages for the buffer device address feature. - nir_opt_large_constants generates stateless messages. - XeHP curbe setup can generate stateless messages. So counting stateless messages is not accurate. Instead, we move the spill/fill accounting to the register allocator, as it generates such things, as well as the load/store_scratch intrinsic handling, as those are basically spill/fills, just at a higher level. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16691>
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@@ -348,10 +348,10 @@ private:
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void build_interference_graph(bool allow_spilling);
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void discard_interference_graph();
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void emit_unspill(const fs_builder &bld, fs_reg dst,
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uint32_t spill_offset, unsigned count);
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void emit_spill(const fs_builder &bld, fs_reg src,
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uint32_t spill_offset, unsigned count);
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void emit_unspill(const fs_builder &bld, struct shader_stats *stats,
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fs_reg dst, uint32_t spill_offset, unsigned count);
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void emit_spill(const fs_builder &bld, struct shader_stats *stats,
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fs_reg src, uint32_t spill_offset, unsigned count);
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void set_spill_costs();
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int choose_spill_reg();
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@@ -738,7 +738,9 @@ fs_reg_alloc::discard_interference_graph()
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}
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void
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fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
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fs_reg_alloc::emit_unspill(const fs_builder &bld,
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struct shader_stats *stats,
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fs_reg dst,
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uint32_t spill_offset, unsigned count)
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{
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const intel_device_info *devinfo = bld.shader->devinfo;
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@@ -747,6 +749,8 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
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assert(count % reg_size == 0);
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for (unsigned i = 0; i < count / reg_size; i++) {
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++stats->fill_count;
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fs_inst *unspill_inst;
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if (devinfo->ver >= 9) {
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fs_reg header = this->scratch_header;
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@@ -803,7 +807,9 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
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}
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void
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fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
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fs_reg_alloc::emit_spill(const fs_builder &bld,
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struct shader_stats *stats,
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fs_reg src,
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uint32_t spill_offset, unsigned count)
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{
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const intel_device_info *devinfo = bld.shader->devinfo;
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@@ -812,6 +818,8 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
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assert(count % reg_size == 0);
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for (unsigned i = 0; i < count / reg_size; i++) {
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++stats->spill_count;
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fs_inst *spill_inst;
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if (devinfo->ver >= 9) {
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fs_reg header = this->scratch_header;
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@@ -1098,8 +1106,8 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
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* 32 bit channels. It shouldn't hurt in any case because the
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* unspill destination is a block-local temporary.
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*/
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emit_unspill(ibld.exec_all().group(width, 0), unspill_dst,
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subset_spill_offset, count);
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emit_unspill(ibld.exec_all().group(width, 0), &fs->shader_stats,
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unspill_dst, subset_spill_offset, count);
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}
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}
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@@ -1153,10 +1161,10 @@ fs_reg_alloc::spill_reg(unsigned spill_reg)
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*/
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if (inst->is_partial_write() ||
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(!inst->force_writemask_all && !per_channel))
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emit_unspill(ubld, spill_src, subset_spill_offset,
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regs_written(inst));
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emit_unspill(ubld, &fs->shader_stats, spill_src,
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subset_spill_offset, regs_written(inst));
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emit_spill(ubld.at(block, inst->next), spill_src,
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emit_spill(ubld.at(block, inst->next), &fs->shader_stats, spill_src,
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subset_spill_offset, regs_written(inst));
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}
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