Move the intel vulkan driver to src/intel/vulkan
This commit is contained in:
Jason Ekstrand
589
src/intel/vulkan/gen7_cmd_buffer.c
Normal file
589
src/intel/vulkan/gen7_cmd_buffer.c
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@@ -0,0 +1,589 @@
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen7_pack.h"
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#include "genxml/gen75_pack.h"
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static uint32_t
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cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
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{
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static const uint32_t push_constant_opcodes[] = {
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[MESA_SHADER_VERTEX] = 21,
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[MESA_SHADER_TESS_CTRL] = 25, /* HS */
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[MESA_SHADER_TESS_EVAL] = 26, /* DS */
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[MESA_SHADER_GEOMETRY] = 22,
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[MESA_SHADER_FRAGMENT] = 23,
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[MESA_SHADER_COMPUTE] = 0,
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};
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VkShaderStageFlags flushed = 0;
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anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
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if (stage == MESA_SHADER_COMPUTE)
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continue;
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struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
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if (state.offset == 0)
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continue;
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CONSTANT_VS,
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._3DCommandSubOpcode = push_constant_opcodes[stage],
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.ConstantBody = {
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.PointerToConstantBuffer0 = { .offset = state.offset },
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.ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
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});
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flushed |= mesa_to_vk_shader_stage(stage);
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}
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cmd_buffer->state.push_constants_dirty &= ~flushed;
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return flushed;
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}
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GENX_FUNC(GEN7, GEN7) void
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genX(cmd_buffer_emit_descriptor_pointers)(struct anv_cmd_buffer *cmd_buffer,
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uint32_t stages)
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{
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static const uint32_t sampler_state_opcodes[] = {
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[MESA_SHADER_VERTEX] = 43,
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[MESA_SHADER_TESS_CTRL] = 44, /* HS */
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[MESA_SHADER_TESS_EVAL] = 45, /* DS */
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[MESA_SHADER_GEOMETRY] = 46,
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[MESA_SHADER_FRAGMENT] = 47,
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[MESA_SHADER_COMPUTE] = 0,
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};
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static const uint32_t binding_table_opcodes[] = {
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[MESA_SHADER_VERTEX] = 38,
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[MESA_SHADER_TESS_CTRL] = 39,
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[MESA_SHADER_TESS_EVAL] = 40,
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[MESA_SHADER_GEOMETRY] = 41,
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[MESA_SHADER_FRAGMENT] = 42,
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[MESA_SHADER_COMPUTE] = 0,
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};
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anv_foreach_stage(s, stages) {
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if (cmd_buffer->state.samplers[s].alloc_size > 0) {
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anv_batch_emit(&cmd_buffer->batch,
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GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
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._3DCommandSubOpcode = sampler_state_opcodes[s],
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.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
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}
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/* Always emit binding table pointers if we're asked to, since on SKL
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* this is what flushes push constants. */
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anv_batch_emit(&cmd_buffer->batch,
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GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
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._3DCommandSubOpcode = binding_table_opcodes[s],
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.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
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}
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}
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GENX_FUNC(GEN7, GEN7) uint32_t
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genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer)
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{
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VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
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cmd_buffer->state.pipeline->active_stages;
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VkResult result = VK_SUCCESS;
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anv_foreach_stage(s, dirty) {
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result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
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&cmd_buffer->state.samplers[s]);
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if (result != VK_SUCCESS)
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break;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
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&cmd_buffer->state.binding_tables[s]);
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if (result != VK_SUCCESS)
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break;
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}
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if (result != VK_SUCCESS) {
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assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
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result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
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assert(result == VK_SUCCESS);
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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/* Re-emit all active binding tables */
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dirty |= cmd_buffer->state.pipeline->active_stages;
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anv_foreach_stage(s, dirty) {
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result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
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&cmd_buffer->state.samplers[s]);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
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&cmd_buffer->state.binding_tables[s]);
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if (result != VK_SUCCESS)
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return result;
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}
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}
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cmd_buffer->state.descriptors_dirty &= ~dirty;
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return dirty;
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}
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static inline int64_t
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clamp_int64(int64_t x, int64_t min, int64_t max)
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{
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if (x < min)
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return min;
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else if (x < max)
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return x;
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else
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return max;
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}
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static void
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emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
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uint32_t count, const VkRect2D *scissors)
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{
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struct anv_state scissor_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
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for (uint32_t i = 0; i < count; i++) {
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const VkRect2D *s = &scissors[i];
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/* Since xmax and ymax are inclusive, we have to have xmax < xmin or
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* ymax < ymin for empty clips. In case clip x, y, width height are all
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* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
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* what we want. Just special case empty clips and produce a canonical
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* empty clip. */
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static const struct GEN7_SCISSOR_RECT empty_scissor = {
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.ScissorRectangleYMin = 1,
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.ScissorRectangleXMin = 1,
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.ScissorRectangleYMax = 0,
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.ScissorRectangleXMax = 0
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};
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const int max = 0xffff;
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struct GEN7_SCISSOR_RECT scissor = {
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/* Do this math using int64_t so overflow gets clamped correctly. */
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.ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
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.ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
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.ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
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.ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
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};
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if (s->extent.width <= 0 || s->extent.height <= 0) {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
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&empty_scissor);
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} else {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
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}
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}
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
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.ScissorRectPointer = scissor_state.offset);
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(scissor_state);
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}
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GENX_FUNC(GEN7, GEN7) void
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genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->state.dynamic.scissor.count > 0) {
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emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
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cmd_buffer->state.dynamic.scissor.scissors);
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} else {
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/* Emit a default scissor based on the currently bound framebuffer */
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emit_scissor_state(cmd_buffer, 1,
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&(VkRect2D) {
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.offset = { .x = 0, .y = 0, },
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.extent = {
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.width = cmd_buffer->state.framebuffer->width,
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.height = cmd_buffer->state.framebuffer->height,
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},
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});
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}
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}
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static const uint32_t vk_to_gen_index_type[] = {
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[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
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[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
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};
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static const uint32_t restart_index_for_type[] = {
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[VK_INDEX_TYPE_UINT16] = UINT16_MAX,
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[VK_INDEX_TYPE_UINT32] = UINT32_MAX,
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};
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void genX(CmdBindIndexBuffer)(
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VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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if (ANV_IS_HASWELL)
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cmd_buffer->state.restart_index = restart_index_for_type[indexType];
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cmd_buffer->state.gen7.index_buffer = buffer;
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cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
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cmd_buffer->state.gen7.index_offset = offset;
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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MESA_SHADER_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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MESA_SHADER_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
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const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
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const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
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unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
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unsigned push_constant_data_size =
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(prog_data->nr_params + local_id_dwords) * 4;
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unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
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unsigned push_constant_regs = reg_aligned_constant_size / 32;
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if (push_state.alloc_size) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
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.CURBETotalDataLength = push_state.alloc_size,
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.CURBEDataStartAddress = push_state.offset);
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}
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assert(prog_data->total_shared <= 64 * 1024);
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uint32_t slm_size = 0;
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if (prog_data->total_shared > 0) {
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/* slm_size is in 4k increments, but must be a power of 2. */
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slm_size = 4 * 1024;
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while (slm_size < prog_data->total_shared)
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slm_size <<= 1;
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slm_size /= 4 * 1024;
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}
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GEN7_INTERFACE_DESCRIPTOR_DATA, 64,
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.KernelStartPointer = pipeline->cs_simd,
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.BindingTablePointer = surfaces.offset,
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.SamplerStatePointer = samplers.offset,
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.ConstantURBEntryReadLength =
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push_constant_regs,
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.ConstantURBEntryReadOffset = 0,
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.BarrierEnable = cs_prog_data->uses_barrier,
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.SharedLocalMemorySize = slm_size,
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.NumberofThreadsinGPGPUThreadGroup =
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pipeline->cs_thread_width_max);
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const uint32_t size = GEN7_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
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anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
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.InterfaceDescriptorTotalLength = size,
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.InterfaceDescriptorDataStartAddress = state.offset);
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return VK_SUCCESS;
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}
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void
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genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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if (cmd_buffer->state.current_pipeline != GPGPU) {
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
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.PipelineSelection = GPGPU);
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cmd_buffer->state.current_pipeline = GPGPU;
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}
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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/* FIXME: figure out descriptors for gen7 */
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result = flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
|
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}
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|
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cmd_buffer->state.compute_dirty = 0;
|
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}
|
||||
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void
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genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
|
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{
|
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struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
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uint32_t *p;
|
||||
|
||||
uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
|
||||
|
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assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
|
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|
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genX(flush_pipeline_select_3d)(cmd_buffer);
|
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|
||||
if (vb_emit) {
|
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const uint32_t num_buffers = __builtin_popcount(vb_emit);
|
||||
const uint32_t num_dwords = 1 + num_buffers * 4;
|
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|
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p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
|
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GEN7_3DSTATE_VERTEX_BUFFERS);
|
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uint32_t vb, i = 0;
|
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for_each_bit(vb, vb_emit) {
|
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struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
|
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uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
|
||||
|
||||
struct GEN7_VERTEX_BUFFER_STATE state = {
|
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.VertexBufferIndex = vb,
|
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.BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
|
||||
.VertexBufferMemoryObjectControlState = GEN7_MOCS,
|
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.AddressModifyEnable = true,
|
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.BufferPitch = pipeline->binding_stride[vb],
|
||||
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
||||
.EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
|
||||
.InstanceDataStepRate = 1
|
||||
};
|
||||
|
||||
GEN7_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
|
||||
/* If somebody compiled a pipeline after starting a command buffer the
|
||||
* scratch bo may have grown since we started this cmd buffer (and
|
||||
* emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
|
||||
* reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
|
||||
if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
|
||||
gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
|
||||
|
||||
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
|
||||
cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
|
||||
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
|
||||
*
|
||||
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
|
||||
* stall needs to be sent just prior to any 3DSTATE_VS,
|
||||
* 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
|
||||
* 3DSTATE_BINDING_TABLE_POINTER_VS,
|
||||
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
|
||||
* PIPE_CONTROL needs to be sent before any combination of VS
|
||||
* associated 3DSTATE."
|
||||
*/
|
||||
anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
|
||||
.DepthStallEnable = true,
|
||||
.PostSyncOperation = WriteImmediateData,
|
||||
.Address = { &cmd_buffer->device->workaround_bo, 0 });
|
||||
}
|
||||
|
||||
uint32_t dirty = 0;
|
||||
if (cmd_buffer->state.descriptors_dirty) {
|
||||
dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
|
||||
gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.push_constants_dirty)
|
||||
cmd_buffer_flush_push_constants(cmd_buffer);
|
||||
|
||||
/* We use the gen8 state here because it only contains the additional
|
||||
* min/max fields and, since they occur at the end of the packet and
|
||||
* don't change the stride, they work on gen7 too.
|
||||
*/
|
||||
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
|
||||
gen8_cmd_buffer_emit_viewport(cmd_buffer);
|
||||
|
||||
if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
|
||||
gen7_cmd_buffer_emit_scissor(cmd_buffer);
|
||||
|
||||
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||
ANV_CMD_DIRTY_RENDER_TARGETS |
|
||||
ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
|
||||
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
|
||||
|
||||
bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
|
||||
cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
|
||||
|
||||
const struct anv_image_view *iview =
|
||||
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
|
||||
const struct anv_image *image = iview ? iview->image : NULL;
|
||||
const uint32_t depth_format = image ?
|
||||
isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
|
||||
&image->depth_surface.isl) : D16_UNORM;
|
||||
|
||||
uint32_t sf_dw[GEN7_3DSTATE_SF_length];
|
||||
struct GEN7_3DSTATE_SF sf = {
|
||||
GEN7_3DSTATE_SF_header,
|
||||
.DepthBufferSurfaceFormat = depth_format,
|
||||
.LineWidth = cmd_buffer->state.dynamic.line_width,
|
||||
.GlobalDepthOffsetEnableSolid = enable_bias,
|
||||
.GlobalDepthOffsetEnableWireframe = enable_bias,
|
||||
.GlobalDepthOffsetEnablePoint = enable_bias,
|
||||
.GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
|
||||
.GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
|
||||
.GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
|
||||
};
|
||||
GEN7_3DSTATE_SF_pack(NULL, sf_dw, &sf);
|
||||
|
||||
anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
|
||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
|
||||
struct anv_state cc_state =
|
||||
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
||||
GEN7_COLOR_CALC_STATE_length * 4,
|
||||
64);
|
||||
struct GEN7_COLOR_CALC_STATE cc = {
|
||||
.BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
|
||||
.BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
|
||||
.BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
|
||||
.BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
|
||||
.StencilReferenceValue =
|
||||
cmd_buffer->state.dynamic.stencil_reference.front,
|
||||
.BackFaceStencilReferenceValue =
|
||||
cmd_buffer->state.dynamic.stencil_reference.back,
|
||||
};
|
||||
GEN7_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
|
||||
if (!cmd_buffer->device->info.has_llc)
|
||||
anv_state_clflush(cc_state);
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch,
|
||||
GEN7_3DSTATE_CC_STATE_POINTERS,
|
||||
.ColorCalcStatePointer = cc_state.offset);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||
ANV_CMD_DIRTY_RENDER_TARGETS |
|
||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
||||
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
|
||||
uint32_t depth_stencil_dw[GEN7_DEPTH_STENCIL_STATE_length];
|
||||
|
||||
const struct anv_image_view *iview =
|
||||
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
|
||||
|
||||
struct GEN7_DEPTH_STENCIL_STATE depth_stencil = {
|
||||
.StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
|
||||
|
||||
.StencilTestMask =
|
||||
cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
|
||||
.StencilWriteMask =
|
||||
cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
|
||||
|
||||
.BackfaceStencilTestMask =
|
||||
cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
|
||||
.BackfaceStencilWriteMask =
|
||||
cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
|
||||
};
|
||||
GEN7_DEPTH_STENCIL_STATE_pack(NULL, depth_stencil_dw, &depth_stencil);
|
||||
|
||||
struct anv_state ds_state =
|
||||
anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
|
||||
pipeline->gen7.depth_stencil_state,
|
||||
GEN7_DEPTH_STENCIL_STATE_length, 64);
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch,
|
||||
GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
|
||||
.PointertoDEPTH_STENCIL_STATE = ds_state.offset);
|
||||
}
|
||||
|
||||
if (cmd_buffer->state.gen7.index_buffer &&
|
||||
cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
||||
ANV_CMD_DIRTY_INDEX_BUFFER)) {
|
||||
struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
|
||||
uint32_t offset = cmd_buffer->state.gen7.index_offset;
|
||||
|
||||
if (ANV_IS_HASWELL) {
|
||||
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
|
||||
.IndexedDrawCutIndexEnable = pipeline->primitive_restart,
|
||||
.CutIndex = cmd_buffer->state.restart_index);
|
||||
}
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
|
||||
.CutIndexEnable = pipeline->primitive_restart,
|
||||
.IndexFormat = cmd_buffer->state.gen7.index_type,
|
||||
.MemoryObjectControlState = GEN7_MOCS,
|
||||
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
||||
.BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
|
||||
}
|
||||
|
||||
cmd_buffer->state.vb_dirty &= ~vb_emit;
|
||||
cmd_buffer->state.dirty = 0;
|
||||
}
|
||||
|
||||
void genX(CmdSetEvent)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkEvent event,
|
||||
VkPipelineStageFlags stageMask)
|
||||
{
|
||||
stub();
|
||||
}
|
||||
|
||||
void genX(CmdResetEvent)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkEvent event,
|
||||
VkPipelineStageFlags stageMask)
|
||||
{
|
||||
stub();
|
||||
}
|
||||
|
||||
void genX(CmdWaitEvents)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
uint32_t eventCount,
|
||||
const VkEvent* pEvents,
|
||||
VkPipelineStageFlags srcStageMask,
|
||||
VkPipelineStageFlags destStageMask,
|
||||
uint32_t memoryBarrierCount,
|
||||
const VkMemoryBarrier* pMemoryBarriers,
|
||||
uint32_t bufferMemoryBarrierCount,
|
||||
const VkBufferMemoryBarrier* pBufferMemoryBarriers,
|
||||
uint32_t imageMemoryBarrierCount,
|
||||
const VkImageMemoryBarrier* pImageMemoryBarriers)
|
||||
{
|
||||
stub();
|
||||
}
|
||||
Reference in New Issue
Block a user