diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e6e209f79a0..15b94e04e2f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3961,8 +3961,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags dst_flag
 }
 
 void
-radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass *subpass,
-                         const struct radv_subpass_barrier *barrier)
+radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
+                          const struct radv_subpass_barrier *barrier)
 {
    struct radv_render_pass *pass = cmd_buffer->state.pass;
 
@@ -5721,7 +5721,7 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpa
 
    ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4096);
 
-   radv_emit_subpass_barrier(cmd_buffer, subpass, &subpass->start_barrier);
+   radv_emit_subpass_barrier(cmd_buffer, &subpass->start_barrier);
 
    radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
 
@@ -7280,8 +7280,7 @@ radv_CmdEndRenderPass2(VkCommandBuffer commandBuffer, const VkSubpassEndInfo *pS
 
    radv_mark_noncoherent_rb(cmd_buffer);
 
-   radv_emit_subpass_barrier(cmd_buffer, cmd_buffer->state.subpass,
-                             &cmd_buffer->state.pass->end_barrier);
+   radv_emit_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
 
    radv_cmd_buffer_end_subpass(cmd_buffer);
 
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index b2440e108d2..0e8bad1dde0 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -795,7 +795,7 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
    barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
    barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
    barrier.dst_access_mask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT;
-   radv_emit_subpass_barrier(cmd_buffer, subpass, &barrier);
+   radv_emit_subpass_barrier(cmd_buffer, &barrier);
 
    for (uint32_t i = 0; i < subpass->color_count; ++i) {
       struct radv_subpass_attachment src_att = subpass->color_attachments[i];
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 50d86768c64..1733dce702f 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -1078,7 +1078,7 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
    barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
    barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
    barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
-   radv_emit_subpass_barrier(cmd_buffer, subpass, &barrier);
+   radv_emit_subpass_barrier(cmd_buffer, &barrier);
 
    radv_decompress_resolve_subpass_src(cmd_buffer);
 
@@ -1131,7 +1131,7 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
    barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
    barrier.src_access_mask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
    barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
-   radv_emit_subpass_barrier(cmd_buffer, subpass, &barrier);
+   radv_emit_subpass_barrier(cmd_buffer, &barrier);
 
    struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
    struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 7654da11070..306a2965da8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2422,7 +2422,6 @@ struct radv_subpass_barrier {
 };
 
 void radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
-                               const struct radv_subpass *subpass,
                                const struct radv_subpass_barrier *barrier);
 
 struct radv_subpass_attachment {