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anv: Rework setting primitive topology

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For one thing, we were deceptively setting it wrong in genX_cmd_buffer.c
and then overwriting it in each of of gfx7_cmd_buffer.c and
gfx8_cmd_buffer.c.  Pull it all into genX_cmd_buffer.c so it's no longer
duplicated.  Also, stop doing the PATCHLIST conversion in anv_pipeline.c
and just store the number of patch vertices.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17564>
This commit is contained in:
Jason Ekstrand
2022-07-14 11:41:17 -05:00
committed by Marge Bot
parent b656957c56
commit 97dd1a100d
5 changed files with 22 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
src/intel/vulkan/anv_pipeline.c
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@@ -35,7 +35,6 @@
#include "anv_private.h"
#include "compiler/brw_nir.h"
#include "compiler/brw_nir_rt.h"
#include "compiler/brw_prim.h"
#include "anv_nir.h"
#include "nir/nir_xfb_info.h"
#include "spirv/nir_spirv.h"
@@ -270,19 +269,6 @@ void anv_DestroyPipeline(
vk_free2(&device->vk.alloc, pAllocator, pipeline);
}
static const uint32_t vk_to_intel_primitive_type[] = {
[VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
[VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
[VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
};
static void
populate_sampler_prog_key(const struct intel_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
@@ -2325,14 +2311,6 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline,
pipeline->instance_multiplier = 1;
if (pipeline->view_mask && !pipeline->use_primitive_replication)
pipeline->instance_multiplier = util_bitcount(pipeline->view_mask);
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
pipeline->topology =
_3DPRIM_PATCHLIST(state->ts->patch_control_points);
} else {
pipeline->topology =
vk_to_intel_primitive_type[state->ia->primitive_topology];
}
} else {
assert(anv_pipeline_is_mesh(pipeline));
/* TODO(mesh): Mesh vs. Multiview with Instancing. */
@@ -2352,6 +2330,8 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline,
pipeline->line_mode = VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT;
}
}
pipeline->patch_control_points =
state->ts != NULL ? state->ts->patch_control_points : 0;
/* Store the color write masks, to be merged with color write enable if
* dynamic.

3
src/intel/vulkan/anv_private.h
View File

@@ -3322,13 +3322,12 @@ struct anv_graphics_pipeline {
struct anv_dynamic_state non_dynamic_state;
uint32_t topology;
/* These fields are required with dynamic primitive topology,
* rasterization_samples used only with gen < 8.
*/
VkLineRasterizationModeEXT line_mode;
VkPolygonMode polygon_mode;
uint32_t patch_control_points;
uint32_t rasterization_samples;
VkColorComponentFlags color_comp_writes[MAX_RTS];

22
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -37,6 +37,7 @@
#include "genxml/genX_pack.h"
#include "genxml/gen_rt_pack.h"
#include "common/intel_guardband.h"
#include "compiler/brw_prim.h"
#include "nir/nir_xfb_info.h"
@@ -3899,9 +3900,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer_alloc_push_constants(cmd_buffer);
}
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
cmd_buffer->state.gfx.primitive_topology = pipeline->topology;
#if GFX_VER <= 7
if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
@@ -3985,6 +3983,24 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
ANV_CMD_DIRTY_DYNAMIC_VIEWPORT))
cmd_buffer_emit_scissor(cmd_buffer);
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
const struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
uint32_t topology;
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
topology = _3DPRIM_PATCHLIST(pipeline->patch_control_points);
else
topology = genX(vk_to_intel_primitive_type)[d->primitive_topology];
cmd_buffer->state.gfx.primitive_topology = topology;
#if (GFX_VER >= 8)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
vft.PrimitiveTopologyType = topology;
}
#endif
}
genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
}

11
src/intel/vulkan/gfx7_cmd_buffer.c
View File

@@ -62,17 +62,6 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
uint32_t topology;
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
topology = pipeline->topology;
else
topology = genX(vk_to_intel_primitive_type)[d->primitive_topology];
cmd_buffer->state.gfx.primitive_topology = topology;
}
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_RENDER_TARGETS |
ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |

15
src/intel/vulkan/gfx8_cmd_buffer.c
View File

@@ -328,21 +328,6 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
genX(emit_shading_rate)(&cmd_buffer->batch, pipeline, d);
#endif /* GFX_VER >= 11 */
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
uint32_t topology;
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
topology = pipeline->topology;
else
topology = genX(vk_to_intel_primitive_type)[d->primitive_topology];
cmd_buffer->state.gfx.primitive_topology = topology;
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
vft.PrimitiveTopologyType = topology;
}
}
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
uint32_t sf_dw[GENX(3DSTATE_SF_length)];