diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 92aab57920a..5e524ceb7b6 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1061,11 +1061,9 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 	surf->surf_size = out.surfSize;
 	surf->surf_alignment = out.baseAlign;
 
-	if (in->swizzleMode == ADDR_SW_LINEAR) {
-		for (unsigned i = 0; i < in->numMipLevels; i++) {
-			surf->u.gfx9.offset[i] = mip_info[i].offset;
-			surf->u.gfx9.pitch[i] = mip_info[i].pitch;
-		}
+	for (unsigned i = 0; i < in->numMipLevels; i++) {
+		surf->u.gfx9.offset[i] = mip_info[i].offset;
+		surf->u.gfx9.pitch[i] = mip_info[i].pitch;
 	}
 
 	if (in->flags.depth) {
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 1e90c08b2e5..dec7b206a6a 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -152,9 +152,9 @@ struct gfx9_surf_layout {
     uint64_t                    surf_offset; /* 0 unless imported with an offset */
     /* The size of the 2D plane containing all mipmap levels. */
     uint64_t                    surf_slice_size;
-    /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
+    /* Mipmap level offset within the slice in bytes. */
     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
-    /* Mipmap level pitch in elements. Only valid for LINEAR. */
+    /* Mipmap level pitch in elements. */
     uint32_t                    pitch[RADEON_SURF_MAX_LEVELS];
 
     uint64_t                    stencil_offset; /* separate stencil */