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anv/pipeline: Follow push constant alignment restrictions on BDW+ and HSW gt3

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This commit is contained in:
Jason Ekstrand
2016-02-29 14:13:56 -08:00
parent 6986ae35ad
commit 9715724015
1 changed files with 8 additions and 1 deletions
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9
src/intel/vulkan/anv_pipeline.c
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@@ -894,9 +894,16 @@ gen7_compute_urb_partition(struct anv_pipeline *pipeline)
const unsigned stages = const unsigned stages =
_mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS); _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
const unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0; unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
unsigned used_kb = 0; unsigned used_kb = 0;
/* Broadwell+ and Haswell gt3 require that the push constant sizes be in
* units of 2KB. Incidentally, these are the same platforms that have
* 32KB worth of push constant space.
*/
if (push_constant_kb == 32)
size_per_stage &= ~1u;
for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) { for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
pipeline->urb.push_size[i] = pipeline->urb.push_size[i] =
(pipeline->active_stages & (1 << i)) ? size_per_stage : 0; (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;