diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index 1eafb614474..a36a7694104 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -215,10 +215,10 @@ iris_init_batch(struct iris_context *ice,
 
    if (INTEL_DEBUG) {
       const unsigned decode_flags =
-         GEN_BATCH_DECODE_FULL |
-         ((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
-         GEN_BATCH_DECODE_OFFSETS |
-         GEN_BATCH_DECODE_FLOATS;
+         INTEL_BATCH_DECODE_FULL |
+         ((INTEL_DEBUG & DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
+         INTEL_BATCH_DECODE_OFFSETS |
+         INTEL_BATCH_DECODE_FLOATS;
 
       intel_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
                                   stderr, decode_flags, NULL,
diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c
index a17942859d9..01fad9d0d7c 100644
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -169,11 +169,11 @@ iris_get_sample_position(struct pipe_context *ctx,
       } v;
    } u;
    switch (sample_count) {
-   case 1:  GEN_SAMPLE_POS_1X(u.v._);  break;
-   case 2:  GEN_SAMPLE_POS_2X(u.v._);  break;
-   case 4:  GEN_SAMPLE_POS_4X(u.v._);  break;
-   case 8:  GEN_SAMPLE_POS_8X(u.v._);  break;
-   case 16: GEN_SAMPLE_POS_16X(u.v._); break;
+   case 1:  INTEL_SAMPLE_POS_1X(u.v._);  break;
+   case 2:  INTEL_SAMPLE_POS_2X(u.v._);  break;
+   case 4:  INTEL_SAMPLE_POS_4X(u.v._);  break;
+   case 8:  INTEL_SAMPLE_POS_8X(u.v._);  break;
+   case 16: INTEL_SAMPLE_POS_16X(u.v._); break;
    default: unreachable("invalid sample count");
    }
 
@@ -349,9 +349,9 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 
    int priority = 0;
    if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
-      priority = GEN_CONTEXT_HIGH_PRIORITY;
+      priority = INTEL_CONTEXT_HIGH_PRIORITY;
    if (flags & PIPE_CONTEXT_LOW_PRIORITY)
-      priority = GEN_CONTEXT_LOW_PRIORITY;
+      priority = INTEL_CONTEXT_LOW_PRIORITY;
 
    if (INTEL_DEBUG & DEBUG_BATCH)
       ice->state.sizes = _mesa_hash_table_u64_create(ice);
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index f2a0c695a0d..92d2ba5b7fe 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -758,7 +758,7 @@ iris_emit_l3_config(struct iris_batch *batch,
 
    iris_pack_state(L3_ALLOCATION_REG, &reg_val, reg) {
 #if GEN_GEN < 11
-      reg.SLMEnable = cfg->n[GEN_L3P_SLM] > 0;
+      reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
 #endif
 #if GEN_GEN == 11
       /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
@@ -769,10 +769,10 @@ iris_emit_l3_config(struct iris_batch *batch,
       reg.UseFullWays = true;
 #endif
       if (GEN_GEN < 12 || cfg) {
-         reg.URBAllocation = cfg->n[GEN_L3P_URB];
-         reg.ROAllocation = cfg->n[GEN_L3P_RO];
-         reg.DCAllocation = cfg->n[GEN_L3P_DC];
-         reg.AllAllocation = cfg->n[GEN_L3P_ALL];
+         reg.URBAllocation = cfg->n[INTEL_L3P_URB];
+         reg.ROAllocation = cfg->n[INTEL_L3P_RO];
+         reg.DCAllocation = cfg->n[INTEL_L3P_DC];
+         reg.AllAllocation = cfg->n[INTEL_L3P_ALL];
       } else {
 #if GEN_GEN >= 12
          reg.L3FullWayAllocationEnable = true;
@@ -1068,12 +1068,12 @@ iris_init_render_context(struct iris_batch *batch)
 
    /* Set the initial MSAA sample positions. */
    iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
-      GEN_SAMPLE_POS_1X(pat._1xSample);
-      GEN_SAMPLE_POS_2X(pat._2xSample);
-      GEN_SAMPLE_POS_4X(pat._4xSample);
-      GEN_SAMPLE_POS_8X(pat._8xSample);
+      INTEL_SAMPLE_POS_1X(pat._1xSample);
+      INTEL_SAMPLE_POS_2X(pat._2xSample);
+      INTEL_SAMPLE_POS_4X(pat._4xSample);
+      INTEL_SAMPLE_POS_8X(pat._8xSample);
 #if GEN_GEN >= 9
-      GEN_SAMPLE_POS_16X(pat._16xSample);
+      INTEL_SAMPLE_POS_16X(pat._16xSample);
 #endif
    }
 
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index e379b5cfb7b..d507eafbbb2 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1239,22 +1239,22 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
 
       switch (params->num_samples) {
       case 1:
-         GEN_SAMPLE_POS_1X(ms.Sample);
+         INTEL_SAMPLE_POS_1X(ms.Sample);
          break;
       case 2:
-         GEN_SAMPLE_POS_2X(ms.Sample);
+         INTEL_SAMPLE_POS_2X(ms.Sample);
          break;
       case 4:
-         GEN_SAMPLE_POS_4X(ms.Sample);
+         INTEL_SAMPLE_POS_4X(ms.Sample);
          break;
       case 8:
-         GEN_SAMPLE_POS_8X(ms.Sample);
+         INTEL_SAMPLE_POS_8X(ms.Sample);
          break;
       default:
          break;
       }
 #else
-      GEN_SAMPLE_POS_4X(ms.Sample);
+      INTEL_SAMPLE_POS_4X(ms.Sample);
 #endif
       ms.PixelLocation              = CENTER;
    }
diff --git a/src/intel/common/intel_aux_map.c b/src/intel/common/intel_aux_map.c
index 8560d152c82..07844201d2b 100644
--- a/src/intel/common/intel_aux_map.c
+++ b/src/intel/common/intel_aux_map.c
@@ -310,7 +310,7 @@ get_bpp_encoding(enum isl_format format)
    }
 }
 
-#define GEN_AUX_MAP_ENTRY_Y_TILED_BIT  (0x1ull << 52)
+#define INTEL_AUX_MAP_ENTRY_Y_TILED_BIT  (0x1ull << 52)
 
 uint64_t
 intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
@@ -327,9 +327,9 @@ intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
       ((uint64_t)isl_format_get_aux_map_encoding(format) << 58) |
       ((uint64_t)(plane > 0) << 57) |
       ((uint64_t)get_bpp_encoding(format) << 54) |
-      GEN_AUX_MAP_ENTRY_Y_TILED_BIT;
+      INTEL_AUX_MAP_ENTRY_Y_TILED_BIT;
 
-   assert((format_bits & GEN_AUX_MAP_FORMAT_BITS_MASK) == format_bits);
+   assert((format_bits & INTEL_AUX_MAP_FORMAT_BITS_MASK) == format_bits);
 
    return format_bits;
 }
@@ -350,7 +350,7 @@ get_aux_entry(struct intel_aux_map_context *ctx, uint64_t address,
    uint64_t *l3_entry = &ctx->level3_map[l3_index];
 
    uint64_t *l2_map;
-   if ((*l3_entry & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((*l3_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       uint64_t l2_gpu;
       if (add_sub_table(ctx, 32 * 1024, 32 * 1024, &l2_gpu, &l2_map)) {
          if (aux_map_debug)
@@ -368,7 +368,7 @@ get_aux_entry(struct intel_aux_map_context *ctx, uint64_t address,
    uint64_t *l2_entry = &l2_map[l2_index];
 
    uint64_t l1_addr, *l1_map;
-   if ((*l2_entry & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((*l2_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       if (add_sub_table(ctx, 8 * 1024, 8 * 1024, &l1_addr, &l1_map)) {
          if (aux_map_debug)
             fprintf(stderr, "AUX-MAP L2[0x%x]: 0x%"PRIx64", map=%p\n",
@@ -404,12 +404,12 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t address,
    get_aux_entry(ctx, address, &l1_index, NULL, &l1_entry);
 
    const uint64_t l1_data =
-      (aux_address & GEN_AUX_MAP_ADDRESS_MASK) |
+      (aux_address & INTEL_AUX_MAP_ADDRESS_MASK) |
       format_bits |
-      GEN_AUX_MAP_ENTRY_VALID_BIT;
+      INTEL_AUX_MAP_ENTRY_VALID_BIT;
 
    const uint64_t current_l1_data = *l1_entry;
-   if ((current_l1_data & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       assert((aux_address & 0xffULL) == 0);
       if (aux_map_debug)
          fprintf(stderr, "AUX-MAP L1[0x%x] 0x%"PRIx64" -> 0x%"PRIx64"\n",
@@ -421,7 +421,7 @@ add_mapping(struct intel_aux_map_context *ctx, uint64_t address,
        * aux-map tables to be flushed.
        */
       if (current_l1_data != 0 && \
-          (current_l1_data | GEN_AUX_MAP_ENTRY_VALID_BIT) != l1_data)
+          (current_l1_data | INTEL_AUX_MAP_ENTRY_VALID_BIT) != l1_data)
          *state_changed = true;
       *l1_entry = l1_data;
    } else {
@@ -454,12 +454,12 @@ intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t address,
    pthread_mutex_lock(&ctx->mutex);
    uint64_t map_addr = address;
    uint64_t dest_aux_addr = aux_address;
-   assert(align64(address, GEN_AUX_MAP_MAIN_PAGE_SIZE) == address);
-   assert(align64(aux_address, GEN_AUX_MAP_AUX_PAGE_SIZE) == aux_address);
+   assert(align64(address, INTEL_AUX_MAP_MAIN_PAGE_SIZE) == address);
+   assert(align64(aux_address, INTEL_AUX_MAP_AUX_PAGE_SIZE) == aux_address);
    while (map_addr - address < main_size_B) {
       add_mapping(ctx, map_addr, dest_aux_addr, format_bits, &state_changed);
-      map_addr += GEN_AUX_MAP_MAIN_PAGE_SIZE;
-      dest_aux_addr += GEN_AUX_MAP_AUX_PAGE_SIZE;
+      map_addr += INTEL_AUX_MAP_MAIN_PAGE_SIZE;
+      dest_aux_addr += INTEL_AUX_MAP_AUX_PAGE_SIZE;
    }
    pthread_mutex_unlock(&ctx->mutex);
    if (state_changed)
@@ -480,7 +480,7 @@ remove_mapping(struct intel_aux_map_context *ctx, uint64_t address,
    uint64_t *l3_entry = &ctx->level3_map[l3_index];
 
    uint64_t *l2_map;
-   if ((*l3_entry & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((*l3_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       return;
    } else {
       uint64_t l2_addr = intel_canonical_address(*l3_entry & ~0x7fffULL);
@@ -490,7 +490,7 @@ remove_mapping(struct intel_aux_map_context *ctx, uint64_t address,
    uint64_t *l2_entry = &l2_map[l2_index];
 
    uint64_t *l1_map;
-   if ((*l2_entry & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((*l2_entry & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       return;
    } else {
       uint64_t l1_addr = intel_canonical_address(*l2_entry & ~0x1fffULL);
@@ -502,7 +502,7 @@ remove_mapping(struct intel_aux_map_context *ctx, uint64_t address,
    const uint64_t current_l1_data = *l1_entry;
    const uint64_t l1_data = current_l1_data & ~1ull;
 
-   if ((current_l1_data & GEN_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+   if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
       return;
    } else {
       if (aux_map_debug)
@@ -530,7 +530,7 @@ intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t address,
               address + size);
 
    uint64_t map_addr = address;
-   assert(align64(address, GEN_AUX_MAP_MAIN_PAGE_SIZE) == address);
+   assert(align64(address, INTEL_AUX_MAP_MAIN_PAGE_SIZE) == address);
    while (map_addr - address < size) {
       remove_mapping(ctx, map_addr, &state_changed);
       map_addr += 64 * 1024;
diff --git a/src/intel/common/intel_aux_map.h b/src/intel/common/intel_aux_map.h
index 7f58f308f2e..0d9bd45809a 100644
--- a/src/intel/common/intel_aux_map.h
+++ b/src/intel/common/intel_aux_map.h
@@ -43,13 +43,13 @@ extern "C" {
 struct intel_aux_map_context;
 struct gen_device_info;
 
-#define GEN_AUX_MAP_ADDRESS_MASK       0x0000ffffffffff00ull
-#define GEN_AUX_MAP_FORMAT_BITS_MASK   0xfff0000000000000ull
-#define GEN_AUX_MAP_ENTRY_VALID_BIT    0x1ull
-#define GEN_AUX_MAP_GEN12_CCS_SCALE    256
-#define GEN_AUX_MAP_MAIN_PAGE_SIZE     (64 * 1024)
-#define GEN_AUX_MAP_AUX_PAGE_SIZE \
-   (GEN_AUX_MAP_MAIN_PAGE_SIZE / GEN_AUX_MAP_GEN12_CCS_SCALE)
+#define INTEL_AUX_MAP_ADDRESS_MASK       0x0000ffffffffff00ull
+#define INTEL_AUX_MAP_FORMAT_BITS_MASK   0xfff0000000000000ull
+#define INTEL_AUX_MAP_ENTRY_VALID_BIT    0x1ull
+#define INTEL_AUX_MAP_GEN12_CCS_SCALE    256
+#define INTEL_AUX_MAP_MAIN_PAGE_SIZE     (64 * 1024)
+#define INTEL_AUX_MAP_AUX_PAGE_SIZE \
+   (INTEL_AUX_MAP_MAIN_PAGE_SIZE / INTEL_AUX_MAP_GEN12_CCS_SCALE)
 
 struct intel_aux_map_context *
 intel_aux_map_init(void *driver_ctx,
diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c
index 700e3fda288..0b4ce252a96 100644
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -75,7 +75,7 @@ ctx_print_group(struct intel_batch_decode_ctx *ctx,
                 uint64_t address, const void *map)
 {
    intel_print_group(ctx->fp, group, address, map, 0,
-                   (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) != 0);
+                   (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) != 0);
 }
 
 static struct intel_batch_decode_bo
@@ -189,7 +189,7 @@ ctx_print_buffer(struct intel_batch_decode_ctx *ctx,
       }
       fprintf(ctx->fp, column_count == 0 ? "  " : " ");
 
-      if ((ctx->flags & GEN_BATCH_DECODE_FLOATS) && probably_float(*dw))
+      if ((ctx->flags & INTEL_BATCH_DECODE_FLOATS) && probably_float(*dw))
          fprintf(ctx->fp, "  %8.2f", *(float *) dw);
       else
          fprintf(ctx->fp, "  0x%08x", *dw);
@@ -1084,12 +1084,12 @@ intel_print_batch(struct intel_batch_decode_ctx *ctx,
    const uint32_t *p, *end = batch + batch_size / sizeof(uint32_t);
    int length;
    struct intel_group *inst;
-   const char *reset_color = ctx->flags & GEN_BATCH_DECODE_IN_COLOR ? NORMAL : "";
+   const char *reset_color = ctx->flags & INTEL_BATCH_DECODE_IN_COLOR ? NORMAL : "";
 
    if (ctx->n_batch_buffer_start >= 100) {
       fprintf(ctx->fp, "%s0x%08"PRIx64": Max batch buffer jumps exceeded%s\n",
-              (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
-              (ctx->flags & GEN_BATCH_DECODE_OFFSETS) ? batch_addr : 0,
+              (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
+              (ctx->flags & INTEL_BATCH_DECODE_OFFSETS) ? batch_addr : 0,
               reset_color);
       return;
    }
@@ -1103,19 +1103,19 @@ intel_print_batch(struct intel_batch_decode_ctx *ctx,
       length = MAX2(1, length);
 
       uint64_t offset;
-      if (ctx->flags & GEN_BATCH_DECODE_OFFSETS)
+      if (ctx->flags & INTEL_BATCH_DECODE_OFFSETS)
          offset = batch_addr + ((char *)p - (char *)batch);
       else
          offset = 0;
 
       if (inst == NULL) {
          fprintf(ctx->fp, "%s0x%08"PRIx64": unknown instruction %08x%s\n",
-                 (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
+                 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
                  offset, p[0], reset_color);
 
          for (int i=1; i < length; i++) {
             fprintf(ctx->fp, "%s0x%08"PRIx64": -- %08x%s\n",
-                 (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
+                 (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) ? RED_COLOR : "",
                  offset + i * 4, p[i], reset_color);
          }
 
@@ -1124,9 +1124,9 @@ intel_print_batch(struct intel_batch_decode_ctx *ctx,
 
       const char *color;
       const char *inst_name = intel_group_get_name(inst);
-      if (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) {
+      if (ctx->flags & INTEL_BATCH_DECODE_IN_COLOR) {
          reset_color = NORMAL;
-         if (ctx->flags & GEN_BATCH_DECODE_FULL) {
+         if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
             if (strcmp(inst_name, "MI_BATCH_BUFFER_START") == 0 ||
                 strcmp(inst_name, "MI_BATCH_BUFFER_END") == 0)
                color = GREEN_HEADER;
@@ -1143,7 +1143,7 @@ intel_print_batch(struct intel_batch_decode_ctx *ctx,
       fprintf(ctx->fp, "%s0x%08"PRIx64":  0x%08x:  %-80s%s\n",
               color, offset, p[0], inst_name, reset_color);
 
-      if (ctx->flags & GEN_BATCH_DECODE_FULL) {
+      if (ctx->flags & INTEL_BATCH_DECODE_FULL) {
          ctx_print_group(ctx, inst, offset, p);
 
          for (int i = 0; i < ARRAY_SIZE(custom_decoders); i++) {
diff --git a/src/intel/common/intel_decoder.c b/src/intel/common/intel_decoder.c
index 1dab245e9c9..6d3f634a31f 100644
--- a/src/intel/common/intel_decoder.c
+++ b/src/intel/common/intel_decoder.c
@@ -282,27 +282,27 @@ string_to_type(struct parser_context *ctx, const char *s)
    struct intel_enum *e;
 
    if (strcmp(s, "int") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_INT };
+      return (struct intel_type) { .kind = INTEL_TYPE_INT };
    else if (strcmp(s, "uint") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_UINT };
+      return (struct intel_type) { .kind = INTEL_TYPE_UINT };
    else if (strcmp(s, "bool") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_BOOL };
+      return (struct intel_type) { .kind = INTEL_TYPE_BOOL };
    else if (strcmp(s, "float") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_FLOAT };
+      return (struct intel_type) { .kind = INTEL_TYPE_FLOAT };
    else if (strcmp(s, "address") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_ADDRESS };
+      return (struct intel_type) { .kind = INTEL_TYPE_ADDRESS };
    else if (strcmp(s, "offset") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_OFFSET };
+      return (struct intel_type) { .kind = INTEL_TYPE_OFFSET };
    else if (sscanf(s, "u%d.%d", &i, &f) == 2)
-      return (struct intel_type) { .kind = GEN_TYPE_UFIXED, .i = i, .f = f };
+      return (struct intel_type) { .kind = INTEL_TYPE_UFIXED, .i = i, .f = f };
    else if (sscanf(s, "s%d.%d", &i, &f) == 2)
-      return (struct intel_type) { .kind = GEN_TYPE_SFIXED, .i = i, .f = f };
+      return (struct intel_type) { .kind = INTEL_TYPE_SFIXED, .i = i, .f = f };
    else if (g = intel_spec_find_struct(ctx->spec, s), g != NULL)
-      return (struct intel_type) { .kind = GEN_TYPE_STRUCT, .intel_struct = g };
+      return (struct intel_type) { .kind = INTEL_TYPE_STRUCT, .intel_struct = g };
    else if (e = intel_spec_find_enum(ctx->spec, s), e != NULL)
-      return (struct intel_type) { .kind = GEN_TYPE_ENUM, .intel_enum = e };
+      return (struct intel_type) { .kind = INTEL_TYPE_ENUM, .intel_enum = e };
    else if (strcmp(s, "mbo") == 0)
-      return (struct intel_type) { .kind = GEN_TYPE_MBO };
+      return (struct intel_type) { .kind = INTEL_TYPE_MBO };
    else
       fail(&ctx->loc, "invalid type: %s", s);
 }
@@ -1033,8 +1033,8 @@ iter_decode_field_raw(struct intel_field_iterator *iter, uint64_t *qw)
    /* Address & offset types have to be aligned to dwords, their start bit is
     * a reminder of the alignment requirement.
     */
-   if (iter->field->type.kind == GEN_TYPE_ADDRESS ||
-       iter->field->type.kind == GEN_TYPE_OFFSET)
+   if (iter->field->type.kind == INTEL_TYPE_ADDRESS ||
+       iter->field->type.kind == INTEL_TYPE_OFFSET)
       *qw <<= field_start % 32;
 
    return true;
@@ -1062,43 +1062,43 @@ iter_decode_field(struct intel_field_iterator *iter)
 
    v.qw = iter->raw_value;
    switch (iter->field->type.kind) {
-   case GEN_TYPE_UNKNOWN:
-   case GEN_TYPE_INT: {
+   case INTEL_TYPE_UNKNOWN:
+   case INTEL_TYPE_INT: {
       snprintf(iter->value, sizeof(iter->value), "%"PRId64, v.qw);
       enum_name = intel_get_enum_name(&iter->field->inline_enum, v.qw);
       break;
    }
-   case GEN_TYPE_UINT: {
+   case INTEL_TYPE_UINT: {
       snprintf(iter->value, sizeof(iter->value), "%"PRIu64, v.qw);
       enum_name = intel_get_enum_name(&iter->field->inline_enum, v.qw);
       break;
    }
-   case GEN_TYPE_BOOL: {
+   case INTEL_TYPE_BOOL: {
       const char *true_string =
          iter->print_colors ? "\e[0;35mtrue\e[0m" : "true";
       snprintf(iter->value, sizeof(iter->value), "%s",
                v.qw ? true_string : "false");
       break;
    }
-   case GEN_TYPE_FLOAT:
+   case INTEL_TYPE_FLOAT:
       snprintf(iter->value, sizeof(iter->value), "%f", v.f);
       break;
-   case GEN_TYPE_ADDRESS:
-   case GEN_TYPE_OFFSET:
+   case INTEL_TYPE_ADDRESS:
+   case INTEL_TYPE_OFFSET:
       snprintf(iter->value, sizeof(iter->value), "0x%08"PRIx64, v.qw);
       break;
-   case GEN_TYPE_STRUCT:
+   case INTEL_TYPE_STRUCT:
       snprintf(iter->value, sizeof(iter->value), "<struct %s>",
                iter->field->type.intel_struct->name);
       iter->struct_desc =
          intel_spec_find_struct(iter->group->spec,
                                 iter->field->type.intel_struct->name);
       break;
-   case GEN_TYPE_UFIXED:
+   case INTEL_TYPE_UFIXED:
       snprintf(iter->value, sizeof(iter->value), "%f",
                (float) v.qw / (1 << iter->field->type.f));
       break;
-   case GEN_TYPE_SFIXED: {
+   case INTEL_TYPE_SFIXED: {
       /* Sign extend before converting */
       int bits = iter->field->type.i + iter->field->type.f + 1;
       int64_t v_sign_extend = ((int64_t)(v.qw << (64 - bits))) >> (64 - bits);
@@ -1106,9 +1106,9 @@ iter_decode_field(struct intel_field_iterator *iter)
                (float) v_sign_extend / (1 << iter->field->type.f));
       break;
    }
-   case GEN_TYPE_MBO:
+   case INTEL_TYPE_MBO:
        break;
-   case GEN_TYPE_ENUM: {
+   case INTEL_TYPE_ENUM: {
       snprintf(iter->value, sizeof(iter->value), "%"PRId64, v.qw);
       enum_name = intel_get_enum_name(iter->field->type.intel_enum, v.qw);
       break;
diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h
index 720e18f65f9..580d59c3a1a 100644
--- a/src/intel/common/intel_decoder.h
+++ b/src/intel/common/intel_decoder.h
@@ -147,26 +147,26 @@ struct intel_enum {
 
 struct intel_type {
    enum {
-      GEN_TYPE_UNKNOWN,
-      GEN_TYPE_INT,
-      GEN_TYPE_UINT,
-      GEN_TYPE_BOOL,
-      GEN_TYPE_FLOAT,
-      GEN_TYPE_ADDRESS,
-      GEN_TYPE_OFFSET,
-      GEN_TYPE_STRUCT,
-      GEN_TYPE_UFIXED,
-      GEN_TYPE_SFIXED,
-      GEN_TYPE_MBO,
-      GEN_TYPE_ENUM
+      INTEL_TYPE_UNKNOWN,
+      INTEL_TYPE_INT,
+      INTEL_TYPE_UINT,
+      INTEL_TYPE_BOOL,
+      INTEL_TYPE_FLOAT,
+      INTEL_TYPE_ADDRESS,
+      INTEL_TYPE_OFFSET,
+      INTEL_TYPE_STRUCT,
+      INTEL_TYPE_UFIXED,
+      INTEL_TYPE_SFIXED,
+      INTEL_TYPE_MBO,
+      INTEL_TYPE_ENUM
    } kind;
 
-   /* Struct definition for  GEN_TYPE_STRUCT */
+   /* Struct definition for  INTEL_TYPE_STRUCT */
    union {
       struct intel_group *intel_struct;
       struct intel_enum *intel_enum;
       struct {
-         /* Integer and fractional sizes for GEN_TYPE_UFIXED and GEN_TYPE_SFIXED */
+         /* Integer and fractional sizes for INTEL_TYPE_UFIXED and INTEL_TYPE_SFIXED */
          int i, f;
       };
    };
@@ -207,13 +207,13 @@ void intel_print_group(FILE *out,
 
 enum intel_batch_decode_flags {
    /** Print in color! */
-   GEN_BATCH_DECODE_IN_COLOR  = (1 << 0),
+   INTEL_BATCH_DECODE_IN_COLOR  = (1 << 0),
    /** Print everything, not just headers */
-   GEN_BATCH_DECODE_FULL      = (1 << 1),
+   INTEL_BATCH_DECODE_FULL      = (1 << 1),
    /** Print offsets along with the batch */
-   GEN_BATCH_DECODE_OFFSETS   = (1 << 2),
+   INTEL_BATCH_DECODE_OFFSETS   = (1 << 2),
    /** Guess when a value is a float and print it as such */
-   GEN_BATCH_DECODE_FLOATS    = (1 << 3),
+   INTEL_BATCH_DECODE_FLOATS    = (1 << 3),
 };
 
 struct intel_batch_decode_bo {
diff --git a/src/intel/common/intel_defines.h b/src/intel/common/intel_defines.h
index 5a870ce3167..2715db7821b 100644
--- a/src/intel/common/intel_defines.h
+++ b/src/intel/common/intel_defines.h
@@ -36,16 +36,16 @@ extern "C" {
  * Common defines we want to share between GL And Vulkan.
  */
 
-#define GEN_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
-#define GEN_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
-#define GEN_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
+#define INTEL_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
+#define INTEL_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
+#define INTEL_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
 /* We don't have a strict notion of RT (yet, and when we do it is likely
  * to be more complicated than a mere priority value!), but we can give
  * it the absolute most priority available to us. By convention, this
  * is higher than any other client, except for blocked interactive
  * clients.
  */
-#define GEN_CONTEXT_REALTIME_PRIORITY I915_CONTEXT_MAX_USER_PRIORITY
+#define INTEL_CONTEXT_REALTIME_PRIORITY I915_CONTEXT_MAX_USER_PRIORITY
 
 #ifdef __cplusplus
 }
diff --git a/src/intel/common/intel_l3_config.c b/src/intel/common/intel_l3_config.c
index 3ea90b18fdb..6f15e4db71b 100644
--- a/src/intel/common/intel_l3_config.c
+++ b/src/intel/common/intel_l3_config.c
@@ -197,10 +197,10 @@ norm_l3_weights(struct intel_l3_weights w)
 {
    float sz = 0;
 
-   for (unsigned i = 0; i < GEN_NUM_L3P; i++)
+   for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
       sz += w.w[i];
 
-   for (unsigned i = 0; i < GEN_NUM_L3P; i++)
+   for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
       w.w[i] /= sz;
 
    return w;
@@ -215,7 +215,7 @@ intel_get_l3_config_weights(const struct intel_l3_config *cfg)
    if (cfg) {
       struct intel_l3_weights w;
 
-      for (unsigned i = 0; i < GEN_NUM_L3P; i++)
+      for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
          w.w[i] = cfg->n[i];
 
       return norm_l3_weights(w);
@@ -236,15 +236,15 @@ intel_get_l3_config_weights(const struct intel_l3_config *cfg)
 float
 intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1)
 {
-   if ((w0.w[GEN_L3P_SLM] && !w1.w[GEN_L3P_SLM]) ||
-       (w0.w[GEN_L3P_DC] && !w1.w[GEN_L3P_DC] && !w1.w[GEN_L3P_ALL]) ||
-       (w0.w[GEN_L3P_URB] && !w1.w[GEN_L3P_URB])) {
+   if ((w0.w[INTEL_L3P_SLM] && !w1.w[INTEL_L3P_SLM]) ||
+       (w0.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_ALL]) ||
+       (w0.w[INTEL_L3P_URB] && !w1.w[INTEL_L3P_URB])) {
       return HUGE_VALF;
 
    } else {
       float dw = 0;
 
-      for (unsigned i = 0; i < GEN_NUM_L3P; i++)
+      for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
          dw += fabsf(w0.w[i] - w1.w[i]);
 
       return dw;
@@ -262,14 +262,14 @@ intel_get_default_l3_weights(const struct gen_device_info *devinfo,
 {
    struct intel_l3_weights w = {{ 0 }};
 
-   w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
-   w.w[GEN_L3P_URB] = 1.0;
+   w.w[INTEL_L3P_SLM] = devinfo->gen < 11 && needs_slm;
+   w.w[INTEL_L3P_URB] = 1.0;
 
    if (devinfo->gen >= 8) {
-      w.w[GEN_L3P_ALL] = 1.0;
+      w.w[INTEL_L3P_ALL] = 1.0;
    } else {
-      w.w[GEN_L3P_DC] = needs_dc ? 0.1 : 0;
-      w.w[GEN_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
+      w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0;
+      w.w[INTEL_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
    }
 
    return norm_l3_weights(w);
@@ -364,7 +364,7 @@ intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
     * only 1008KB of this will be used."
     */
    const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
-   return MIN2(max, cfg->n[GEN_L3P_URB] * get_l3_way_size(devinfo)) /
+   return MIN2(max, cfg->n[INTEL_L3P_URB] * get_l3_way_size(devinfo)) /
           get_urb_size_scale(devinfo);
 }
 
@@ -375,7 +375,7 @@ void
 intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp)
 {
    fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
-           cfg->n[GEN_L3P_SLM], cfg->n[GEN_L3P_URB], cfg->n[GEN_L3P_ALL],
-           cfg->n[GEN_L3P_DC], cfg->n[GEN_L3P_RO],
-           cfg->n[GEN_L3P_IS], cfg->n[GEN_L3P_C], cfg->n[GEN_L3P_T]);
+           cfg->n[INTEL_L3P_SLM], cfg->n[INTEL_L3P_URB], cfg->n[INTEL_L3P_ALL],
+           cfg->n[INTEL_L3P_DC], cfg->n[INTEL_L3P_RO],
+           cfg->n[INTEL_L3P_IS], cfg->n[INTEL_L3P_C], cfg->n[INTEL_L3P_T]);
 }
diff --git a/src/intel/common/intel_l3_config.h b/src/intel/common/intel_l3_config.h
index 2a26bfe8b27..0cf89501346 100644
--- a/src/intel/common/intel_l3_config.h
+++ b/src/intel/common/intel_l3_config.h
@@ -33,23 +33,23 @@
  */
 enum intel_l3_partition {
    /** Shared local memory. */
-   GEN_L3P_SLM = 0,
+   INTEL_L3P_SLM = 0,
    /** Unified return buffer. */
-   GEN_L3P_URB,
+   INTEL_L3P_URB,
    /** Union of DC and RO. */
-   GEN_L3P_ALL,
+   INTEL_L3P_ALL,
    /** Data cluster RW partition. */
-   GEN_L3P_DC,
+   INTEL_L3P_DC,
    /** Union of IS, C and T. */
-   GEN_L3P_RO,
+   INTEL_L3P_RO,
    /** Instruction and state cache. */
-   GEN_L3P_IS,
+   INTEL_L3P_IS,
    /** Constant cache. */
-   GEN_L3P_C,
+   INTEL_L3P_C,
    /** Texture cache. */
-   GEN_L3P_T,
+   INTEL_L3P_T,
    /** Number of supported L3 partitions. */
-   GEN_NUM_L3P
+   INTEL_NUM_L3P
 };
 
 /**
@@ -57,7 +57,7 @@ enum intel_l3_partition {
  * partition.  \sa get_l3_way_size().
  */
 struct intel_l3_config {
-   unsigned n[GEN_NUM_L3P];
+   unsigned n[INTEL_NUM_L3P];
 };
 
 /**
@@ -67,7 +67,7 @@ struct intel_l3_config {
  * configuration.
  */
 struct intel_l3_weights {
-   float w[GEN_NUM_L3P];
+   float w[INTEL_NUM_L3P];
 };
 
 float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1);
@@ -93,9 +93,9 @@ intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
 void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
 
 enum intel_urb_deref_block_size {
-   GEN_URB_DEREF_BLOCK_SIZE_32         = 0,
-   GEN_URB_DEREF_BLOCK_SIZE_PER_POLY   = 1,
-   GEN_URB_DEREF_BLOCK_SIZE_8          = 2,
+   INTEL_URB_DEREF_BLOCK_SIZE_32         = 0,
+   INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY   = 1,
+   INTEL_URB_DEREF_BLOCK_SIZE_8          = 2,
 };
 
 void intel_get_urb_config(const struct gen_device_info *devinfo,
diff --git a/src/intel/common/intel_sample_positions.h b/src/intel/common/intel_sample_positions.h
index 0cb51e64b03..0976afd340e 100644
--- a/src/intel/common/intel_sample_positions.h
+++ b/src/intel/common/intel_sample_positions.h
@@ -56,74 +56,74 @@ intel_get_sample_positions(int samples)
 
 /* Examples:
  * in case of GEN_GEN < 8:
- * GEN_SAMPLE_POS_ELEM(ms.Sample, info->pSampleLocations, 0); expands to:
+ * INTEL_SAMPLE_POS_ELEM(ms.Sample, info->pSampleLocations, 0); expands to:
  *    ms.Sample0XOffset = info->pSampleLocations[0].x;
  *    ms.Sample0YOffset = info->pSampleLocations[0].y;
  *
  * in case of GEN_GEN >= 8:
- * GEN_SAMPLE_POS_ELEM(sp._16xSample, info->pSampleLocations, 0); expands to:
+ * INTEL_SAMPLE_POS_ELEM(sp._16xSample, info->pSampleLocations, 0); expands to:
  *    sp._16xSample0XOffset = info->pSampleLocations[0].x;
  *    sp._16xSample0YOffset = info->pSampleLocations[0].y;
  */
 
-#define GEN_SAMPLE_POS_ELEM(prefix, arr, sample_idx) \
+#define INTEL_SAMPLE_POS_ELEM(prefix, arr, sample_idx) \
 prefix##sample_idx##XOffset = arr[sample_idx].x; \
 prefix##sample_idx##YOffset = arr[sample_idx].y;
 
-#define GEN_SAMPLE_POS_1X_ARRAY(prefix, arr)\
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 0);
+#define INTEL_SAMPLE_POS_1X_ARRAY(prefix, arr)\
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 0);
 
-#define GEN_SAMPLE_POS_2X_ARRAY(prefix, arr) \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 0); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 1);
+#define INTEL_SAMPLE_POS_2X_ARRAY(prefix, arr) \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 0); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 1);
 
-#define GEN_SAMPLE_POS_4X_ARRAY(prefix, arr) \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 0); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 1); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 2); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 3);
+#define INTEL_SAMPLE_POS_4X_ARRAY(prefix, arr) \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 0); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 1); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 2); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 3);
 
-#define GEN_SAMPLE_POS_8X_ARRAY(prefix, arr) \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 0); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 1); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 2); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 3); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 4); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 5); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 6); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 7);
+#define INTEL_SAMPLE_POS_8X_ARRAY(prefix, arr) \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 0); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 1); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 2); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 3); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 4); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 5); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 6); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 7);
 
-#define GEN_SAMPLE_POS_16X_ARRAY(prefix, arr) \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 0); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 1); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 2); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 3); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 4); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 5); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 6); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 7); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 8); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 9); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 10); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 11); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 12); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 13); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 14); \
-   GEN_SAMPLE_POS_ELEM(prefix, arr, 15);
+#define INTEL_SAMPLE_POS_16X_ARRAY(prefix, arr) \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 0); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 1); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 2); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 3); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 4); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 5); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 6); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 7); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 8); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 9); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 10); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 11); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 12); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 13); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 14); \
+   INTEL_SAMPLE_POS_ELEM(prefix, arr, 15);
 
-#define GEN_SAMPLE_POS_1X(prefix) \
-   GEN_SAMPLE_POS_1X_ARRAY(prefix, intel_sample_positions_1x)
+#define INTEL_SAMPLE_POS_1X(prefix) \
+   INTEL_SAMPLE_POS_1X_ARRAY(prefix, intel_sample_positions_1x)
 
-#define GEN_SAMPLE_POS_2X(prefix) \
-   GEN_SAMPLE_POS_2X_ARRAY(prefix, intel_sample_positions_2x)
+#define INTEL_SAMPLE_POS_2X(prefix) \
+   INTEL_SAMPLE_POS_2X_ARRAY(prefix, intel_sample_positions_2x)
 
-#define GEN_SAMPLE_POS_4X(prefix) \
-   GEN_SAMPLE_POS_4X_ARRAY(prefix, intel_sample_positions_4x)
+#define INTEL_SAMPLE_POS_4X(prefix) \
+   INTEL_SAMPLE_POS_4X_ARRAY(prefix, intel_sample_positions_4x)
 
-#define GEN_SAMPLE_POS_8X(prefix) \
-   GEN_SAMPLE_POS_8X_ARRAY(prefix, intel_sample_positions_8x)
+#define INTEL_SAMPLE_POS_8X(prefix) \
+   INTEL_SAMPLE_POS_8X_ARRAY(prefix, intel_sample_positions_8x)
 
-#define GEN_SAMPLE_POS_16X(prefix) \
-   GEN_SAMPLE_POS_16X_ARRAY(prefix, intel_sample_positions_16x)
+#define INTEL_SAMPLE_POS_16X(prefix) \
+   INTEL_SAMPLE_POS_16X_ARRAY(prefix, intel_sample_positions_16x)
 
 #endif /* INTEL_SAMPLE_POSITIONS_H */
diff --git a/src/intel/common/intel_urb_config.c b/src/intel/common/intel_urb_config.c
index 97ce4e8fbad..b6a5260319b 100644
--- a/src/intel/common/intel_urb_config.c
+++ b/src/intel/common/intel_urb_config.c
@@ -256,17 +256,17 @@ intel_get_urb_config(const struct gen_device_info *devinfo,
           * not in one of the explicit cases listed above.
           */
          if (gs_present) {
-            *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+            *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
          } else if (tess_present) {
             if (entries[MESA_SHADER_TESS_EVAL] < 324)
-               *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+               *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
             else
-               *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_32;
+               *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
          } else {
             if (entries[MESA_SHADER_VERTEX] < 192)
-               *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+               *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
             else
-               *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_32;
+               *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
          }
       } else {
          *deref_block_size = 0;
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index b7f94a41e53..dcf3d32b192 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -85,12 +85,12 @@ aubinator_init(void *user_data, int aub_pci_id, const char *app_name)
 
    enum intel_batch_decode_flags batch_flags = 0;
    if (option_color == COLOR_ALWAYS)
-      batch_flags |= GEN_BATCH_DECODE_IN_COLOR;
+      batch_flags |= INTEL_BATCH_DECODE_IN_COLOR;
    if (option_full_decode)
-      batch_flags |= GEN_BATCH_DECODE_FULL;
+      batch_flags |= INTEL_BATCH_DECODE_FULL;
    if (option_print_offsets)
-      batch_flags |= GEN_BATCH_DECODE_OFFSETS;
-   batch_flags |= GEN_BATCH_DECODE_FLOATS;
+      batch_flags |= INTEL_BATCH_DECODE_OFFSETS;
+   batch_flags |= INTEL_BATCH_DECODE_FLOATS;
 
    intel_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, batch_flags,
                                xml_path, NULL, NULL, NULL);
diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c
index 62e8a88e5df..0b948deb7ec 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -654,12 +654,12 @@ read_data_file(FILE *file)
 
    enum intel_batch_decode_flags batch_flags = 0;
    if (option_color == COLOR_ALWAYS)
-      batch_flags |= GEN_BATCH_DECODE_IN_COLOR;
+      batch_flags |= INTEL_BATCH_DECODE_IN_COLOR;
    if (option_full_decode)
-      batch_flags |= GEN_BATCH_DECODE_FULL;
+      batch_flags |= INTEL_BATCH_DECODE_FULL;
    if (option_print_offsets)
-      batch_flags |= GEN_BATCH_DECODE_OFFSETS;
-   batch_flags |= GEN_BATCH_DECODE_FLOATS;
+      batch_flags |= INTEL_BATCH_DECODE_OFFSETS;
+   batch_flags |= INTEL_BATCH_DECODE_FLOATS;
 
    struct intel_batch_decode_ctx batch_ctx;
    intel_batch_decode_ctx_init(&batch_ctx, &devinfo, stdout, batch_flags,
@@ -680,7 +680,7 @@ read_data_file(FILE *file)
           strcmp(sections[s].buffer_name, "batch buffer") == 0 ||
           strcmp(sections[s].buffer_name, "HW Context") == 0) {
          if (is_ring_buffer && ring_wraps)
-            batch_ctx.flags &= ~GEN_BATCH_DECODE_OFFSETS;
+            batch_ctx.flags &= ~INTEL_BATCH_DECODE_OFFSETS;
          batch_ctx.engine = class;
          uint8_t *data = (uint8_t *)sections[s].data + sections[s].data_offset;
          uint64_t batch_addr = sections[s].gtt_offset + sections[s].data_offset;
diff --git a/src/intel/tools/aubinator_viewer_decoder.cpp b/src/intel/tools/aubinator_viewer_decoder.cpp
index 234ce336113..3844300eb8a 100644
--- a/src/intel/tools/aubinator_viewer_decoder.cpp
+++ b/src/intel/tools/aubinator_viewer_decoder.cpp
@@ -74,7 +74,7 @@ aub_viewer_print_group(struct aub_viewer_decode_ctx *ctx,
       }
       if (!intel_field_is_header(iter.field)) {
          if (ctx->decode_cfg->field_filter.PassFilter(iter.name)) {
-            if (iter.field->type.kind == intel_type::GEN_TYPE_BOOL && iter.raw_value) {
+            if (iter.field->type.kind == intel_type::INTEL_TYPE_BOOL && iter.raw_value) {
                ImGui::Text("%s: ", iter.name); ImGui::SameLine();
                ImGui::TextColored(ctx->cfg->boolean_color, "true");
             } else {
diff --git a/src/intel/tools/gen_context.h b/src/intel/tools/gen_context.h
index 3678d8d6965..d298f55f68d 100644
--- a/src/intel/tools/gen_context.h
+++ b/src/intel/tools/gen_context.h
@@ -21,8 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-#ifndef GEN_CONTEXT_H
-#define GEN_CONTEXT_H
+#ifndef INTEL_CONTEXT_H
+#define INTEL_CONTEXT_H
 
 #include <stdint.h>
 
@@ -101,4 +101,4 @@ typedef void (*gen_context_init_t)(const struct gen_context_parameters *, uint32
 #include "gen8_context.h"
 #include "gen10_context.h"
 
-#endif /* GEN_CONTEXT_H */
+#endif /* INTEL_CONTEXT_H */
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 6f714580d76..433d26af8f6 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1645,7 +1645,7 @@ anv_device_alloc_bo(struct anv_device *device,
       size = align_u64(size, 64 * 1024);
 
       /* See anv_bo::_ccs_size */
-      ccs_size = align_u64(DIV_ROUND_UP(size, GEN_AUX_MAP_GEN12_CCS_SCALE), 4096);
+      ccs_size = align_u64(DIV_ROUND_UP(size, INTEL_AUX_MAP_GEN12_CCS_SCALE), 4096);
    }
 
    uint32_t gem_handle = anv_gem_create(device, size + ccs_size);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4febdbb8ce8..3bed580869b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2751,13 +2751,13 @@ vk_priority_to_gen(int priority)
 {
    switch (priority) {
    case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
-      return GEN_CONTEXT_LOW_PRIORITY;
+      return INTEL_CONTEXT_LOW_PRIORITY;
    case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
-      return GEN_CONTEXT_MEDIUM_PRIORITY;
+      return INTEL_CONTEXT_MEDIUM_PRIORITY;
    case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
-      return GEN_CONTEXT_HIGH_PRIORITY;
+      return INTEL_CONTEXT_HIGH_PRIORITY;
    case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
-      return GEN_CONTEXT_REALTIME_PRIORITY;
+      return INTEL_CONTEXT_REALTIME_PRIORITY;
    default:
       unreachable("Invalid priority");
    }
@@ -2983,10 +2983,10 @@ VkResult anv_CreateDevice(
 
    if (INTEL_DEBUG & DEBUG_BATCH) {
       const unsigned decode_flags =
-         GEN_BATCH_DECODE_FULL |
-         ((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
-         GEN_BATCH_DECODE_OFFSETS |
-         GEN_BATCH_DECODE_FLOATS;
+         INTEL_BATCH_DECODE_FULL |
+         ((INTEL_DEBUG & DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
+         INTEL_BATCH_DECODE_OFFSETS |
+         INTEL_BATCH_DECODE_FLOATS;
 
       intel_batch_decode_ctx_init(&device->decoder_ctx,
                                   &physical_device->info,
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 305f186420b..ae0fb6c7075 100644
--- a/src/intel/vulkan/anv_gem.c
+++ b/src/intel/vulkan/anv_gem.c
@@ -359,7 +359,7 @@ bool
 anv_gem_has_context_priority(int fd)
 {
    return !anv_gem_set_context_param(fd, 0, I915_CONTEXT_PARAM_PRIORITY,
-                                     GEN_CONTEXT_MEDIUM_PRIORITY);
+                                     INTEL_CONTEXT_MEDIUM_PRIORITY);
 }
 
 int
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d291bb57c21..c50b4afca11 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -538,10 +538,10 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
 
          const uint64_t old_aux_entry = READ_ONCE(*aux_entry_map);
          uint64_t new_aux_entry =
-            (old_aux_entry & GEN_AUX_MAP_ADDRESS_MASK) | format_bits;
+            (old_aux_entry & INTEL_AUX_MAP_ADDRESS_MASK) | format_bits;
 
          if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage))
-            new_aux_entry |= GEN_AUX_MAP_ENTRY_VALID_BIT;
+            new_aux_entry |= INTEL_AUX_MAP_ENTRY_VALID_BIT;
 
          mi_store(&b, mi_mem64(aux_entry_address), mi_imm(new_aux_entry));
       }
@@ -1905,7 +1905,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
       intel_dump_l3_config(cfg, stderr);
    }
 
-   UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
+   UNUSED const bool has_slm = cfg->n[INTEL_L3P_SLM];
 
    /* According to the hardware docs, the L3 partitioning can only be changed
     * while the pipeline is completely drained and the caches are flushed,
@@ -1950,7 +1950,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
 
 #if GEN_GEN >= 8
 
-   assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
+   assert(!cfg->n[INTEL_L3P_IS] && !cfg->n[INTEL_L3P_C] && !cfg->n[INTEL_L3P_T]);
 
 #if GEN_GEN >= 12
 #define L3_ALLOCATION_REG GENX(L3ALLOC)
@@ -1973,25 +1973,25 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
                    .ErrorDetectionBehaviorControl = true,
                    .UseFullWays = true,
 #endif
-                   .URBAllocation = cfg->n[GEN_L3P_URB],
-                   .ROAllocation = cfg->n[GEN_L3P_RO],
-                   .DCAllocation = cfg->n[GEN_L3P_DC],
-                   .AllAllocation = cfg->n[GEN_L3P_ALL]);
+                   .URBAllocation = cfg->n[INTEL_L3P_URB],
+                   .ROAllocation = cfg->n[INTEL_L3P_RO],
+                   .DCAllocation = cfg->n[INTEL_L3P_DC],
+                   .AllAllocation = cfg->n[INTEL_L3P_ALL]);
 
    /* Set up the L3 partitioning. */
    emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr);
 
 #else
 
-   const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
-   const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
-                       cfg->n[GEN_L3P_ALL];
-   const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
-                      cfg->n[GEN_L3P_ALL];
-   const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
-                      cfg->n[GEN_L3P_ALL];
+   const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
+   const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
+                       cfg->n[INTEL_L3P_ALL];
+   const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
+                      cfg->n[INTEL_L3P_ALL];
+   const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] ||
+                      cfg->n[INTEL_L3P_ALL];
 
-   assert(!cfg->n[GEN_L3P_ALL]);
+   assert(!cfg->n[INTEL_L3P_ALL]);
 
    /* When enabled SLM only uses a portion of the L3 on half of the banks,
     * the matching space on the remaining banks has to be allocated to a
@@ -2000,11 +2000,11 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
     */
    const struct gen_device_info *devinfo = &cmd_buffer->device->info;
    const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
-   assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
+   assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
 
    /* Minimum number of ways that can be allocated to the URB. */
    const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0;
-   assert(cfg->n[GEN_L3P_URB] >= n0_urb);
+   assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
 
    uint32_t l3sqcr1, l3cr2, l3cr3;
    anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
@@ -2020,19 +2020,19 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
    anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
                    .SLMEnable = has_slm,
                    .URBLowBandwidth = urb_low_bw,
-                   .URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
+                   .URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb,
 #if !GEN_IS_HASWELL
-                   .ALLAllocation = cfg->n[GEN_L3P_ALL],
+                   .ALLAllocation = cfg->n[INTEL_L3P_ALL],
 #endif
-                   .ROAllocation = cfg->n[GEN_L3P_RO],
-                   .DCAllocation = cfg->n[GEN_L3P_DC]);
+                   .ROAllocation = cfg->n[INTEL_L3P_RO],
+                   .DCAllocation = cfg->n[INTEL_L3P_DC]);
 
    anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
-                   .ISAllocation = cfg->n[GEN_L3P_IS],
+                   .ISAllocation = cfg->n[INTEL_L3P_IS],
                    .ISLowBandwidth = 0,
-                   .CAllocation = cfg->n[GEN_L3P_C],
+                   .CAllocation = cfg->n[INTEL_L3P_C],
                    .CLowBandwidth = 0,
-                   .TAllocation = cfg->n[GEN_L3P_T],
+                   .TAllocation = cfg->n[INTEL_L3P_T],
                    .TLowBandwidth = 0);
 
    /* Set up the L3 partitioning. */
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 47ebb01036d..5b1f3de0177 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -400,16 +400,16 @@ genX(emit_multisample)(struct anv_batch *batch, uint32_t samples,
       if (locations) {
          switch (samples) {
          case 1:
-            GEN_SAMPLE_POS_1X_ARRAY(ms.Sample, locations);
+            INTEL_SAMPLE_POS_1X_ARRAY(ms.Sample, locations);
             break;
          case 2:
-            GEN_SAMPLE_POS_2X_ARRAY(ms.Sample, locations);
+            INTEL_SAMPLE_POS_2X_ARRAY(ms.Sample, locations);
             break;
          case 4:
-            GEN_SAMPLE_POS_4X_ARRAY(ms.Sample, locations);
+            INTEL_SAMPLE_POS_4X_ARRAY(ms.Sample, locations);
             break;
          case 8:
-            GEN_SAMPLE_POS_8X_ARRAY(ms.Sample, locations);
+            INTEL_SAMPLE_POS_8X_ARRAY(ms.Sample, locations);
             break;
          default:
             break;
@@ -417,16 +417,16 @@ genX(emit_multisample)(struct anv_batch *batch, uint32_t samples,
       } else {
          switch (samples) {
          case 1:
-            GEN_SAMPLE_POS_1X(ms.Sample);
+            INTEL_SAMPLE_POS_1X(ms.Sample);
             break;
          case 2:
-            GEN_SAMPLE_POS_2X(ms.Sample);
+            INTEL_SAMPLE_POS_2X(ms.Sample);
             break;
          case 4:
-            GEN_SAMPLE_POS_4X(ms.Sample);
+            INTEL_SAMPLE_POS_4X(ms.Sample);
             break;
          case 8:
-            GEN_SAMPLE_POS_8X(ms.Sample);
+            INTEL_SAMPLE_POS_8X(ms.Sample);
             break;
          default:
             break;
@@ -466,32 +466,32 @@ genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples,
           */
          switch (samples) {
          case 1:
-            GEN_SAMPLE_POS_1X_ARRAY(sp._1xSample, locations);
+            INTEL_SAMPLE_POS_1X_ARRAY(sp._1xSample, locations);
             break;
          case 2:
-            GEN_SAMPLE_POS_2X_ARRAY(sp._2xSample, locations);
+            INTEL_SAMPLE_POS_2X_ARRAY(sp._2xSample, locations);
             break;
          case 4:
-            GEN_SAMPLE_POS_4X_ARRAY(sp._4xSample, locations);
+            INTEL_SAMPLE_POS_4X_ARRAY(sp._4xSample, locations);
             break;
          case 8:
-            GEN_SAMPLE_POS_8X_ARRAY(sp._8xSample, locations);
+            INTEL_SAMPLE_POS_8X_ARRAY(sp._8xSample, locations);
             break;
 #if GEN_GEN >= 9
          case 16:
-            GEN_SAMPLE_POS_16X_ARRAY(sp._16xSample, locations);
+            INTEL_SAMPLE_POS_16X_ARRAY(sp._16xSample, locations);
             break;
 #endif
          default:
             break;
          }
       } else {
-         GEN_SAMPLE_POS_1X(sp._1xSample);
-         GEN_SAMPLE_POS_2X(sp._2xSample);
-         GEN_SAMPLE_POS_4X(sp._4xSample);
-         GEN_SAMPLE_POS_8X(sp._8xSample);
+         INTEL_SAMPLE_POS_1X(sp._1xSample);
+         INTEL_SAMPLE_POS_2X(sp._2xSample);
+         INTEL_SAMPLE_POS_4X(sp._4xSample);
+         INTEL_SAMPLE_POS_8X(sp._8xSample);
 #if GEN_GEN >= 9
-         GEN_SAMPLE_POS_16X(sp._16xSample);
+         INTEL_SAMPLE_POS_16X(sp._16xSample);
 #endif
       }
    }
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 33cfcfafde3..8a38fdb87cd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1072,14 +1072,14 @@ brw_create_context(gl_api api,
    }
 
    if (brw->hw_ctx) {
-      int hw_priority = GEN_CONTEXT_MEDIUM_PRIORITY;
+      int hw_priority = INTEL_CONTEXT_MEDIUM_PRIORITY;
       if (ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_PRIORITY) {
          switch (ctx_config->priority) {
          case __DRI_CTX_PRIORITY_LOW:
-            hw_priority = GEN_CONTEXT_LOW_PRIORITY;
+            hw_priority = INTEL_CONTEXT_LOW_PRIORITY;
             break;
          case __DRI_CTX_PRIORITY_HIGH:
-            hw_priority = GEN_CONTEXT_HIGH_PRIORITY;
+            hw_priority = INTEL_CONTEXT_HIGH_PRIORITY;
             break;
          }
       }
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 915d5d7310f..9285b337244 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -71,14 +71,14 @@ static void
 setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
-   const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
-                       cfg->n[GEN_L3P_ALL];
-   const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
-                      cfg->n[GEN_L3P_ALL];
-   const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
-                      cfg->n[GEN_L3P_ALL];
-   const bool has_slm = cfg->n[GEN_L3P_SLM];
+   const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
+   const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
+                       cfg->n[INTEL_L3P_ALL];
+   const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
+                      cfg->n[INTEL_L3P_ALL];
+   const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] ||
+                      cfg->n[INTEL_L3P_ALL];
+   const bool has_slm = cfg->n[INTEL_L3P_SLM];
 
    /* According to the hardware docs, the L3 partitioning can only be changed
     * while the pipeline is completely drained and the caches are flushed,
@@ -116,20 +116,20 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
                                PIPE_CONTROL_CS_STALL);
 
    if (devinfo->gen >= 8) {
-      assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
+      assert(!cfg->n[INTEL_L3P_IS] && !cfg->n[INTEL_L3P_C] && !cfg->n[INTEL_L3P_T]);
 
       const unsigned imm_data = (
          (devinfo->gen < 11 && has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
          (devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
-         SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
-         SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
-         SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
-         SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
+         SET_FIELD(cfg->n[INTEL_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
+         SET_FIELD(cfg->n[INTEL_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
+         SET_FIELD(cfg->n[INTEL_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
+         SET_FIELD(cfg->n[INTEL_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 
       /* Set up the L3 partitioning. */
       brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
    } else {
-      assert(!cfg->n[GEN_L3P_ALL]);
+      assert(!cfg->n[INTEL_L3P_ALL]);
 
       /* When enabled SLM only uses a portion of the L3 on half of the banks,
        * the matching space on the remaining banks has to be allocated to a
@@ -137,11 +137,11 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
        * lower-bandwidth 2-bank address hashing mode.
        */
       const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
-      assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
+      assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
 
       /* Minimum number of ways that can be allocated to the URB. */
       const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
-      assert(cfg->n[GEN_L3P_URB] >= n0_urb);
+      assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
 
       BEGIN_BATCH(7);
       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
@@ -159,15 +159,15 @@ setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
       /* Set up the L3 partitioning. */
       OUT_BATCH(GEN7_L3CNTLREG2);
       OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
-                SET_FIELD(cfg->n[GEN_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
+                SET_FIELD(cfg->n[INTEL_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
                 (urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
-                SET_FIELD(cfg->n[GEN_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
+                SET_FIELD(cfg->n[INTEL_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
+                SET_FIELD(cfg->n[INTEL_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
+                SET_FIELD(cfg->n[INTEL_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
       OUT_BATCH(GEN7_L3CNTLREG3);
-      OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
+      OUT_BATCH(SET_FIELD(cfg->n[INTEL_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
+                SET_FIELD(cfg->n[INTEL_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
+                SET_FIELD(cfg->n[INTEL_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
 
       ADVANCE_BATCH();
 
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 611a0270b9b..e1e619da263 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3306,20 +3306,20 @@ genX(emit_3dstate_multisample2)(struct brw_context *brw,
       multi.PixelLocation = CENTER;
       multi.NumberofMultisamples = log2_samples;
 #if GEN_GEN == 6
-      GEN_SAMPLE_POS_4X(multi.Sample);
+      INTEL_SAMPLE_POS_4X(multi.Sample);
 #elif GEN_GEN == 7
       switch (num_samples) {
       case 1:
-         GEN_SAMPLE_POS_1X(multi.Sample);
+         INTEL_SAMPLE_POS_1X(multi.Sample);
          break;
       case 2:
-         GEN_SAMPLE_POS_2X(multi.Sample);
+         INTEL_SAMPLE_POS_2X(multi.Sample);
          break;
       case 4:
-         GEN_SAMPLE_POS_4X(multi.Sample);
+         INTEL_SAMPLE_POS_4X(multi.Sample);
          break;
       case 8:
-         GEN_SAMPLE_POS_8X(multi.Sample);
+         INTEL_SAMPLE_POS_8X(multi.Sample);
          break;
       default:
          break;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 49760e71480..b65e34ff89e 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -153,10 +153,10 @@ brw_batch_init(struct brw_context *brw)
          _mesa_hash_table_u64_create(NULL);
 
       const unsigned decode_flags =
-         GEN_BATCH_DECODE_FULL |
-         ((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
-         GEN_BATCH_DECODE_OFFSETS |
-         GEN_BATCH_DECODE_FLOATS;
+         INTEL_BATCH_DECODE_FULL |
+         ((INTEL_DEBUG & DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
+         INTEL_BATCH_DECODE_OFFSETS |
+         INTEL_BATCH_DECODE_FLOATS;
 
       intel_batch_decode_ctx_init(&batch->decoder, devinfo, stderr,
                                   decode_flags, NULL, decode_get_bo,
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index fee6ac3afc7..115880dd2dc 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1585,14 +1585,14 @@ brw_query_renderer_integer(__DRIscreen *dri_screen,
    case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
       value[0] = 0;
       if (brw_hw_context_set_priority(screen->bufmgr,
-                                      0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
+                                      0, INTEL_CONTEXT_HIGH_PRIORITY) == 0)
          value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
       if (brw_hw_context_set_priority(screen->bufmgr,
-                                      0, GEN_CONTEXT_LOW_PRIORITY) == 0)
+                                      0, INTEL_CONTEXT_LOW_PRIORITY) == 0)
          value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
       /* reset to default last, just in case */
       if (brw_hw_context_set_priority(screen->bufmgr,
-                                      0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
+                                      0, INTEL_CONTEXT_MEDIUM_PRIORITY) == 0)
          value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
       return 0;
    case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB: