spirv: Always emit deref_buffer_array_length intrinsics
All the drivers have been converted to setting this option now except imagination and they don't support SSBOs yet. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993 Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
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@@ -762,7 +762,6 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
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.push_const_addr_format = nir_address_format_logical,
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.push_const_addr_format = nir_address_format_logical,
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.shared_addr_format = nir_address_format_32bit_offset,
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.shared_addr_format = nir_address_format_32bit_offset,
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.constant_addr_format = nir_address_format_64bit_global,
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.constant_addr_format = nir_address_format_64bit_global,
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.use_deref_buffer_array_length = true,
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.debug =
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.debug =
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{
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{
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.func = radv_spirv_nir_debug,
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.func = radv_spirv_nir_debug,
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@@ -176,7 +176,6 @@ static const struct spirv_to_nir_options default_spirv_options = {
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.workgroup_memory_explicit_layout = true,
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.workgroup_memory_explicit_layout = true,
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.image_read_without_format = true,
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.image_read_without_format = true,
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},
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},
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.use_deref_buffer_array_length = true,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.phys_ssbo_addr_format = nir_address_format_2x32bit_global,
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.phys_ssbo_addr_format = nir_address_format_2x32bit_global,
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@@ -65,11 +65,6 @@ struct spirv_to_nir_options {
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/* Create a nir library. */
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/* Create a nir library. */
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bool create_library;
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bool create_library;
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/* Whether to use nir_intrinsic_deref_buffer_array_length intrinsic instead
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* of nir_intrinsic_get_ssbo_size to lower OpArrayLength.
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*/
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bool use_deref_buffer_array_length;
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/* Initial value for shader_info::float_controls_execution_mode,
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/* Initial value for shader_info::float_controls_execution_mode,
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* indicates hardware requirements rather than shader author intent
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* indicates hardware requirements rather than shader author intent
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*/
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*/
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@@ -162,7 +162,6 @@ int main(int argc, char **argv)
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struct spirv_to_nir_options spirv_opts = {
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struct spirv_to_nir_options spirv_opts = {
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.environment = env,
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.environment = env,
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.use_deref_buffer_array_length = env == NIR_SPIRV_OPENGL,
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};
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};
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if (shader_stage == MESA_SHADER_KERNEL) {
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if (shader_stage == MESA_SHADER_KERNEL) {
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@@ -2646,7 +2646,6 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
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"OpArrayLength must reference the last memeber of the "
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"OpArrayLength must reference the last memeber of the "
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"structure and that must be an array");
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"structure and that must be an array");
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if (b->options->use_deref_buffer_array_length) {
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struct vtn_access_chain chain = {
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struct vtn_access_chain chain = {
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.length = 1,
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.length = 1,
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.link = {
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.link = {
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@@ -2661,31 +2660,6 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
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.access=ptr->access | ptr->type->access);
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.access=ptr->access | ptr->type->access);
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vtn_push_nir_ssa(b, w[2], array_length);
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vtn_push_nir_ssa(b, w[2], array_length);
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} else {
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const uint32_t offset = ptr->type->offsets[field];
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const uint32_t stride = ptr->type->members[field]->stride;
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if (!ptr->block_index) {
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struct vtn_access_chain chain = {
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.length = 0,
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};
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ptr = vtn_pointer_dereference(b, ptr, &chain);
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vtn_assert(ptr->block_index);
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}
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nir_ssa_def *buf_size = nir_get_ssbo_size(&b->nb, ptr->block_index,
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.access=ptr->access | ptr->type->access);
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/* array_length = max(buffer_size - offset, 0) / stride */
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nir_ssa_def *array_length =
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nir_udiv_imm(&b->nb,
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nir_usub_sat(&b->nb,
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buf_size,
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nir_imm_int(&b->nb, offset)),
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stride);
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vtn_push_nir_ssa(b, w[2], array_length);
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}
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break;
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break;
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}
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}
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@@ -26,7 +26,6 @@ tu_spirv_to_nir(struct tu_device *dev,
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{
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{
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/* TODO these are made-up */
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/* TODO these are made-up */
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const struct spirv_to_nir_options spirv_options = {
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const struct spirv_to_nir_options spirv_options = {
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.use_deref_buffer_array_length = true,
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.ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
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.ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
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.ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
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.ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
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@@ -408,7 +408,6 @@ lvp_shader_compile_to_ir(struct lvp_pipeline *pipeline,
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.float16 = true,
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.float16 = true,
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.demote_to_helper_invocation = true,
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.demote_to_helper_invocation = true,
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},
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},
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.use_deref_buffer_array_length = true,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.phys_ssbo_addr_format = nir_address_format_64bit_global,
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.phys_ssbo_addr_format = nir_address_format_64bit_global,
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@@ -208,7 +208,6 @@ anv_shader_stage_to_nir(struct anv_device *device,
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.workgroup_memory_explicit_layout = true,
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.workgroup_memory_explicit_layout = true,
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.fragment_shading_rate = pdevice->info.ver >= 11,
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.fragment_shading_rate = pdevice->info.ver >= 11,
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},
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},
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.use_deref_buffer_array_length = true,
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.ubo_addr_format =
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.ubo_addr_format =
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anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess),
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anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess),
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.ssbo_addr_format =
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.ssbo_addr_format =
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@@ -114,7 +114,6 @@ anv_shader_stage_to_nir(struct anv_device *device,
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.vk_memory_model_device_scope = true,
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.vk_memory_model_device_scope = true,
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.workgroup_memory_explicit_layout = true,
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.workgroup_memory_explicit_layout = true,
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},
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},
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.use_deref_buffer_array_length = true,
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.ubo_addr_format =
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.ubo_addr_format =
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anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess),
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anv_nir_ubo_addr_format(pdevice, device->vk.enabled_features.robustBufferAccess),
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.ssbo_addr_format =
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.ssbo_addr_format =
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@@ -243,7 +243,6 @@ _mesa_spirv_to_nir(struct gl_context *ctx,
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const struct spirv_to_nir_options spirv_options = {
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const struct spirv_to_nir_options spirv_options = {
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.environment = NIR_SPIRV_OPENGL,
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.environment = NIR_SPIRV_OPENGL,
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.use_deref_buffer_array_length = true,
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.subgroup_size = SUBGROUP_SIZE_UNIFORM,
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.subgroup_size = SUBGROUP_SIZE_UNIFORM,
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.caps = ctx->Const.SpirVCapabilities,
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.caps = ctx->Const.SpirVCapabilities,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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@@ -53,13 +53,6 @@ spirv_to_nir_options = {
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_32bit_index_offset,
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.shared_addr_format = nir_address_format_32bit_offset,
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.shared_addr_format = nir_address_format_32bit_offset,
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/* use_deref_buffer_array_length + nir_lower_explicit_io force
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* get_ssbo_size to take in the return from load_vulkan_descriptor
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* instead of vulkan_resource_index. This makes it much easier to
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* get the DXIL handle for the SSBO.
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*/
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.use_deref_buffer_array_length = true,
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.min_ubo_alignment = 256, /* D3D12_CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT */
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.min_ubo_alignment = 256, /* D3D12_CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT */
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.min_ssbo_alignment = 16, /* D3D12_RAW_UAV_SRV_BYTE_ALIGNMENT */
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.min_ssbo_alignment = 16, /* D3D12_RAW_UAV_SRV_BYTE_ALIGNMENT */
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};
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};
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@@ -241,7 +241,6 @@ panvk_per_arch(shader_create)(struct panvk_device *dev,
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.caps = {
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.caps = {
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.variable_pointers = true,
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.variable_pointers = true,
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},
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},
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.use_deref_buffer_array_length = true,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = dev->vk.enabled_features.robustBufferAccess ?
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.ssbo_addr_format = dev->vk.enabled_features.robustBufferAccess ?
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nir_address_format_64bit_bounded_global :
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nir_address_format_64bit_bounded_global :
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