intel: Use common helpers for TCS passthrough shaders
Rob added these new helpers a while back, which freedreno and radeonsi both share. We should use them too. The new helpers use variables and system value intrinsics, so we can drop the explicit binding table creation and just use the normal paths. Because we have to rewrite the system value uploading anyway, we drop the scrambling of the default tessellation levels on upload, and instead let the compiler go ahead and remap components like any normal shader. In theory, this results in more shuffling in the shader. In practice, we already do MOVs for message setup. In the passthrough shaders I looked at, this resulted in no extra instructions on Icelake (SIMD8 SINGLE_PATCH) and Tigerlake (8_PATCH). On Haswell, one shader grew by a single instruction for a pittance of cycles in a stage that isn't a performance bottleneck anyway. Avoiding remapping wasn't so much of an optimization as just the way that I originally wrote it. Not worth it. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20809>
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@@ -189,9 +189,6 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
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const struct brw_vue_map *vue_map,
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enum tess_primitive_mode tes_primitive_mode)
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{
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const bool is_passthrough_tcs = b->shader->info.name &&
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strcmp(b->shader->info.name, "passthrough TCS") == 0;
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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@@ -203,8 +200,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
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if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
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(stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
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if (!is_passthrough_tcs &&
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remap_tess_levels(b, intrin, tes_primitive_mode))
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if (remap_tess_levels(b, intrin, tes_primitive_mode))
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continue;
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int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
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@@ -1858,50 +1854,21 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile
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{
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const nir_shader_compiler_options *options =
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compiler->nir_options[MESA_SHADER_TESS_CTRL];
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nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_TESS_CTRL,
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options, "passthrough TCS");
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ralloc_steal(mem_ctx, b.shader);
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nir_shader *nir = b.shader;
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nir_variable *var;
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nir_ssa_def *load;
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nir_ssa_def *zero = nir_imm_int(&b, 0);
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nir_ssa_def *invoc_id = nir_load_invocation_id(&b);
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nir->info.inputs_read = key->outputs_written &
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uint64_t inputs_read = key->outputs_written &
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~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
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nir->info.outputs_written = key->outputs_written;
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nir->info.tess.tcs_vertices_out = key->input_vertices;
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nir->num_uniforms = 8 * sizeof(uint32_t);
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var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
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var->data.location = 0;
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var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
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var->data.location = 1;
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unsigned locations[64];
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unsigned num_locations = 0;
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/* Write the patch URB header. */
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for (int i = 0; i <= 1; i++) {
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load = nir_load_uniform(&b, 4, 32, zero, .base = i * 4 * sizeof(uint32_t));
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nir_store_output(&b, load, zero,
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.base = VARYING_SLOT_TESS_LEVEL_INNER - i,
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.write_mask = WRITEMASK_XYZW);
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}
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/* Copy inputs to outputs. */
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uint64_t varyings = nir->info.inputs_read;
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while (varyings != 0) {
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const int varying = ffsll(varyings) - 1;
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load = nir_load_per_vertex_input(&b, 4, 32, invoc_id, zero, .base = varying);
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nir_store_per_vertex_output(&b, load, invoc_id, zero,
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.base = varying,
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.write_mask = WRITEMASK_XYZW);
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varyings &= ~BITFIELD64_BIT(varying);
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}
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u_foreach_bit64(varying, inputs_read)
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locations[num_locations++] = varying;
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nir_shader *nir =
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nir_create_passthrough_tcs_impl(options, locations, num_locations,
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key->input_vertices);
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nir->info.inputs_read = inputs_read;
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nir->info.tess._primitive_mode = key->_tes_primitive_mode;
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nir_validate_shader(nir, "in brw_nir_create_passthrough_tcs");
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struct brw_nir_compiler_opts opts = {};
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