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ac/surface: force linear image layout for chips not supporting image opcodes

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Image opcodes will be emulated.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
This commit is contained in:
Marek Olšák
2022-10-28 08:29:47 -04:00
committed by Marge Bot
parent 8277e6fda3
commit 96913bbf3e
4 changed files with 9 additions and 0 deletions
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3
src/amd/common/ac_gpu_info.c
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@@ -1340,6 +1340,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
} }
info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_MI100; info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_MI100;
info->has_image_opcodes = debug_get_bool_option("AMD_IMAGE_OPCODES",
info->has_graphics || info->family < CHIP_GFX940);
info->never_stop_sq_perf_counters = info->gfx_level == GFX10 || info->never_stop_sq_perf_counters = info->gfx_level == GFX10 ||
info->gfx_level == GFX10_3; info->gfx_level == GFX10_3;
info->never_send_perfcounter_stop = info->gfx_level == GFX11; info->never_send_perfcounter_stop = info->gfx_level == GFX11;
@@ -1612,6 +1614,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug); fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication); fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication);
fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap); fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
fprintf(f, " has_image_opcodes = %i\n", info->has_image_opcodes);
fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters); fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug); fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
fprintf(f, " has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug); fprintf(f, " has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug);

1
src/amd/common/ac_gpu_info.h
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@@ -121,6 +121,7 @@ struct radeon_info {
bool has_cs_regalloc_hang_bug; bool has_cs_regalloc_hang_bug;
bool has_32bit_predication; bool has_32bit_predication;
bool has_3d_cube_border_color_mipmap; bool has_3d_cube_border_color_mipmap;
bool has_image_opcodes;
bool never_stop_sq_perf_counters; bool never_stop_sq_perf_counters;
bool has_sqtt_rb_harvest_bug; bool has_sqtt_rb_harvest_bug;
bool has_sqtt_auto_flush_mode_bug; bool has_sqtt_auto_flush_mode_bug;

4
src/amd/common/ac_surface.c
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@@ -2515,6 +2515,10 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
if (r) if (r)
return r; return r;
/* Images are emulated on some CDNA chips. */
if (!info->has_image_opcodes)
mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
if (info->family_id >= FAMILY_AI) if (info->family_id >= FAMILY_AI)
r = gfx9_compute_surface(addrlib, info, config, mode, surf); r = gfx9_compute_surface(addrlib, info, config, mode, surf);
else else

1
src/amd/vulkan/winsys/null/radv_null_winsys.c
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@@ -128,6 +128,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
info->num_physical_sgprs_per_simd = 512; info->num_physical_sgprs_per_simd = 512;
info->has_3d_cube_border_color_mipmap = true; info->has_3d_cube_border_color_mipmap = true;
info->has_image_opcodes = true;
if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101) if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101)
info->num_physical_wave64_vgprs_per_simd = 768; info->num_physical_wave64_vgprs_per_simd = 768;