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intel/fs: Rework the overlapping mov/vec case

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Now that we're using load/store_reg intrinsics, the previous checks for
registers aren't what we want.  Instead, we need to be looking for a mov
or vec where both the destination and a source are load/store_reg with
matching decl_reg.

Fixes: b8209d69ff ("intel/fs: Add support for new-style registers")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24310>
This commit is contained in:
Faith Ekstrand
2023-07-24 17:32:01 -05:00
committed by Marge Bot
parent 45ee952efb
commit 965bbe5286
1 changed files with 18 additions and 6 deletions
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24
src/intel/compiler/brw_fs_nir.cpp
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@@ -985,12 +985,24 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_vec16: { case nir_op_vec16: {
fs_reg temp = result; fs_reg temp = result;
bool need_extra_copy = false; bool need_extra_copy = false;
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
if (!instr->src[i].src.is_ssa && assert(instr->dest.dest.is_ssa);
instr->dest.dest.reg.reg == instr->src[i].src.reg.reg) { nir_intrinsic_instr *store_reg =
need_extra_copy = true; nir_store_reg_for_def(&instr->dest.dest.ssa);
temp = bld.vgrf(result.type, 4); if (store_reg != NULL) {
break; nir_ssa_def *dest_reg = store_reg->src[1].ssa;
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
assert(instr->src[i].src.is_ssa);
nir_intrinsic_instr *load_reg =
nir_load_reg_for_def(instr->src[i].src.ssa);
if (load_reg == NULL)
continue;
if (load_reg->src[0].ssa == dest_reg) {
need_extra_copy = true;
temp = bld.vgrf(result.type, 4);
break;
}
} }
} }