intel/fs: Break out yet another FB write helper
This new helper, do_emit_fb_writes() does the actual walk over all the render targets to emit each of the different FB writes. We want this in a helper because we're about to go a bit crazy with coarse. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
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@@ -807,6 +807,49 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld,
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return write;
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}
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void
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fs_visitor::do_emit_fb_writes(int nr_color_regions, bool replicate_alpha)
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{
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fs_inst *inst = NULL;
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for (int target = 0; target < nr_color_regions; target++) {
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/* Skip over outputs that weren't written. */
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if (this->outputs[target].file == BAD_FILE)
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continue;
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const fs_builder abld = bld.annotate(
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ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
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fs_reg src0_alpha;
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if (devinfo->ver >= 6 && replicate_alpha && target != 0)
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src0_alpha = offset(outputs[0], bld, 3);
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inst = emit_single_fb_write(abld, this->outputs[target],
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this->dual_src_output, src0_alpha, 4);
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inst->target = target;
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}
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if (inst == NULL) {
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/* Even if there's no color buffers enabled, we still need to send
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* alpha out the pipeline to our null renderbuffer to support
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* alpha-testing, alpha-to-coverage, and so on.
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*/
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/* FINISHME: Factor out this frequently recurring pattern into a
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* helper function.
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*/
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const fs_reg srcs[] = { reg_undef, reg_undef,
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reg_undef, offset(this->outputs[0], bld, 3) };
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const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
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bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
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inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
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inst->target = 0;
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}
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inst->last_rt = true;
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inst->eot = true;
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}
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void
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fs_visitor::emit_fb_writes()
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{
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@@ -814,8 +857,6 @@ fs_visitor::emit_fb_writes()
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struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
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brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
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fs_inst *inst = NULL;
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if (source_depth_to_render_target && devinfo->ver == 6) {
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/* For outputting oDepth on gfx6, SIMD8 writes have to be used. This
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* would require SIMD8 moves of each half to message regs, e.g. by using
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@@ -843,47 +884,10 @@ fs_visitor::emit_fb_writes()
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(key->nr_color_regions > 1 && key->alpha_to_coverage &&
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(sample_mask.file == BAD_FILE || devinfo->ver == 6));
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for (int target = 0; target < key->nr_color_regions; target++) {
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/* Skip over outputs that weren't written. */
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if (this->outputs[target].file == BAD_FILE)
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continue;
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const fs_builder abld = bld.annotate(
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ralloc_asprintf(this->mem_ctx, "FB write target %d", target));
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fs_reg src0_alpha;
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if (devinfo->ver >= 6 && replicate_alpha && target != 0)
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src0_alpha = offset(outputs[0], bld, 3);
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inst = emit_single_fb_write(abld, this->outputs[target],
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this->dual_src_output, src0_alpha, 4);
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inst->target = target;
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}
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prog_data->dual_src_blend = (this->dual_src_output.file != BAD_FILE &&
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this->outputs[0].file != BAD_FILE);
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assert(!prog_data->dual_src_blend || key->nr_color_regions == 1);
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if (inst == NULL) {
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/* Even if there's no color buffers enabled, we still need to send
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* alpha out the pipeline to our null renderbuffer to support
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* alpha-testing, alpha-to-coverage, and so on.
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*/
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/* FINISHME: Factor out this frequently recurring pattern into a
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* helper function.
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*/
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const fs_reg srcs[] = { reg_undef, reg_undef,
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reg_undef, offset(this->outputs[0], bld, 3) };
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const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 4);
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bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
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inst = emit_single_fb_write(bld, tmp, reg_undef, reg_undef, 4);
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inst->target = 0;
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}
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inst->last_rt = true;
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inst->eot = true;
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if (devinfo->ver >= 11 && devinfo->ver <= 12 &&
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prog_data->dual_src_blend) {
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/* The dual-source RT write messages fail to release the thread
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@@ -900,6 +904,8 @@ fs_visitor::emit_fb_writes()
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limit_dispatch_width(8, "Dual source blending unsupported "
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"in SIMD16 and SIMD32 modes.\n");
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}
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do_emit_fb_writes(key->nr_color_regions, replicate_alpha);
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}
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void
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