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i965/vec4: Properly handle sign(-abs(x))

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This is achived by copying the sign(abs(x)) optimization from the FS
backend.

On Gen7 an earlier platforms, this fixes new piglit tests:

 - glsl-1.10/execution/vs-sign-neg-abs.shader_test
 - glsl-1.10/execution/vs-sign-sat-neg-abs.shader_test

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Ian Romanick
2018-06-26 18:30:09 -07:00
parent 88bd37c010
commit 9626ea497d
1 changed files with 17 additions and 1 deletions
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18
src/intel/compiler/brw_vec4_nir.cpp
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@@ -1805,7 +1805,23 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
unreachable("not reached: should have been lowered");
case nir_op_fsign:
if (type_sz(op[0].type) < 8) {
if (op[0].abs) {
/* Straightforward since the source can be assumed to be either
* strictly >= 0 or strictly <= 0 depending on the setting of the
* negate flag.
*/
inst = emit(MOV(dst, op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
inst = (op[0].negate)
? emit(MOV(dst, brw_imm_f(-1.0f)))
: emit(MOV(dst, brw_imm_f(1.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
if (instr->dest.saturate)
inst->saturate = true;
} else if (type_sz(op[0].type) < 8) {
/* AND(val, 0x80000000) gives the sign bit.
*
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not