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ra: Use struct ra_class in the public API.

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All these unsigned ints are awful to keep track of.  Use pointers so we
get some type checking.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
This commit is contained in:
Eric Anholt
2021-03-04 15:14:15 -08:00
committed by Marge Bot
parent 7e0127fb3e
commit 95d41a3525
18 changed files with 126 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/intel/compiler/brw_compiler.h
View File

@@ -50,7 +50,7 @@ struct brw_compiler {
* Array of the ra classes for the unaligned contiguous register
* block sizes used.
*/
int *classes;
struct ra_class **classes;
/**
* Mapping for register-allocated objects in *regs to the first
@@ -66,7 +66,7 @@ struct brw_compiler {
* Array of the ra classes for the unaligned contiguous register
* block sizes used, indexed by register size.
*/
int classes[16];
struct ra_class *classes[16];
/**
* Mapping from classes to ra_reg ranges. Each of the per-size
@@ -88,7 +88,7 @@ struct brw_compiler {
* ra class for the aligned barycentrics we use for PLN, which doesn't
* appear in *classes.
*/
int aligned_bary_class;
struct ra_class *aligned_bary_class;
} fs_reg_sets[3];
void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);

14
src/intel/compiler/brw_fs_reg_allocate.cpp
View File

@@ -154,8 +154,8 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false);
if (devinfo->ver >= 6)
ra_set_allocate_round_robin(regs);
int *classes = ralloc_array(compiler, int, class_count);
int aligned_bary_class = -1;
struct ra_class **classes = ralloc_array(compiler, struct ra_class *, class_count);
struct ra_class *aligned_bary_class = NULL;
/* Allocate space for q values. We allocate class_count + 1 because we
* want to leave room for the aligned barycentric class if we have it.
@@ -221,7 +221,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
if (devinfo->ver <= 5 && dispatch_width >= 16) {
for (int j = 0; j < class_reg_count; j++) {
ra_class_add_reg(regs, classes[i], reg);
ra_class_add_reg(classes[i], reg);
ra_reg_to_grf[reg] = j * 2;
@@ -235,7 +235,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
}
} else {
for (int j = 0; j < class_reg_count; j++) {
ra_class_add_reg(regs, classes[i], reg);
ra_class_add_reg(classes[i], reg);
ra_reg_to_grf[reg] = j;
@@ -266,7 +266,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
for (int i = 0; i < aligned_bary_reg_count; i++) {
if ((ra_reg_to_grf[aligned_bary_base_reg + i] & 1) == 0) {
ra_class_add_reg(regs, aligned_bary_class,
ra_class_add_reg(aligned_bary_class,
aligned_bary_base_reg + i);
}
}
@@ -292,7 +292,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
compiler->fs_reg_sets[index].regs = regs;
for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++)
compiler->fs_reg_sets[index].classes[i] = -1;
compiler->fs_reg_sets[index].classes[i] = NULL;
for (int i = 0; i < class_count; i++)
compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i];
compiler->fs_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf;
@@ -848,7 +848,7 @@ fs_reg_alloc::build_interference_graph(bool allow_spilling)
* of a PLN instruction needs to be an even-numbered register, so we have a
* special register class aligned_bary_class to handle this case.
*/
if (compiler->fs_reg_sets[rsi].aligned_bary_class >= 0) {
if (compiler->fs_reg_sets[rsi].aligned_bary_class) {
foreach_block_and_inst(block, fs_inst, inst, fs->cfg) {
if (inst->opcode == FS_OPCODE_LINTERP && inst->src[0].file == VGRF &&
fs->alloc.sizes[inst->src[0].nr] ==

4
src/intel/compiler/brw_vec4_reg_allocate.cpp
View File

@@ -117,7 +117,7 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
if (compiler->devinfo->ver >= 6)
ra_set_allocate_round_robin(compiler->vec4_reg_set.regs);
ralloc_free(compiler->vec4_reg_set.classes);
compiler->vec4_reg_set.classes = ralloc_array(compiler, int, class_count);
compiler->vec4_reg_set.classes = ralloc_array(compiler, struct ra_class *, class_count);
/* Now, add the registers to their classes, and add the conflicts
* between them and the base GRF registers (and also each other).
@@ -131,7 +131,7 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
q_values[i] = new unsigned[MAX_VGRF_SIZE];
for (int j = 0; j < class_reg_count; j++) {
ra_class_add_reg(compiler->vec4_reg_set.regs, compiler->vec4_reg_set.classes[i], reg);
ra_class_add_reg(compiler->vec4_reg_set.classes[i], reg);
compiler->vec4_reg_set.ra_reg_to_grf[reg] = j;