intel: Add has_bit6_swizzle to devinfo

There's no good reason to have this rather complex check in three
drivers.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13636>

src/gallium/drivers/crocus/crocus_resource.c

@@ -1643,7 +1643,7 @@ crocus_transfer_map(struct pipe_context *ctx,
    memset(map, 0, sizeof(*map));
    map->dbg = &ice->dbg;
 
-   map->has_swizzling = ((struct crocus_screen *)ctx->screen)->has_swizzling;
+   map->has_swizzling = screen->devinfo.has_bit6_swizzle;
    pipe_resource_reference(&xfer->resource, resource);
    xfer->level = level;
    xfer->usage = usage;

src/gallium/drivers/crocus/crocus_screen.c

@@ -708,34 +708,6 @@ crocus_shader_perf_log(void *data, unsigned *id, const char *fmt, ...)
    va_end(args);
 }
 
-static bool
-crocus_detect_swizzling(struct crocus_screen *screen)
-{
-   /* Broadwell PRM says:
-    *
-    *   "Before Gen8, there was a historical configuration control field to
-    *    swizzle address bit[6] for in X/Y tiling modes. This was set in three
-    *    different places: TILECTL[1:0], ARB_MODE[5:4], and
-    *    DISP_ARB_CTL[14:13].
-    *
-    *    For Gen8 and subsequent generations, the swizzle fields are all
-    *    reserved, and the CPU's memory controller performs all address
-    *    swizzling modifications."
-    */
-   uint32_t tiling = I915_TILING_X;
-   uint32_t swizzle_mode = 0;
-   struct crocus_bo *buffer =
-      crocus_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
-                            0, tiling, 512, 0);
-   if (buffer == NULL)
-      return false;
-
-   crocus_bo_get_tiling(buffer, &tiling, &swizzle_mode);
-   crocus_bo_unreference(buffer);
-
-   return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
-}
-
 struct pipe_screen *
 crocus_screen_create(int fd, const struct pipe_screen_config *config)
 {
@@ -780,7 +752,6 @@ crocus_screen_create(int fd, const struct pipe_screen_config *config)
    screen->fd = crocus_bufmgr_get_fd(screen->bufmgr);
    screen->winsys_fd = fd;
 
-   screen->has_swizzling = crocus_detect_swizzling(screen);
    brw_process_intel_debug_variable();
 
    screen->driconf.dual_color_blend_by_location =
@@ -792,8 +763,7 @@ crocus_screen_create(int fd, const struct pipe_screen_config *config)
 
    screen->precompile = env_var_as_boolean("shader_precompile", true);
 
-   isl_device_init(&screen->isl_dev, &screen->devinfo,
+   isl_device_init(&screen->isl_dev, &screen->devinfo);
-                   screen->has_swizzling);
 
    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
    screen->compiler->shader_debug_log = crocus_shader_debug_log;

src/gallium/drivers/crocus/crocus_screen.h

@@ -208,7 +208,6 @@ struct crocus_screen {
    struct crocus_bufmgr *bufmgr;
    struct brw_compiler *compiler;
    struct crocus_monitor_config *monitor_cfg;
-   bool has_swizzling;
 
    const struct intel_l3_config *l3_config_3d;
    const struct intel_l3_config *l3_config_cs;

src/gallium/drivers/iris/iris_screen.c

@@ -825,7 +825,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
 
    screen->precompile = env_var_as_boolean("shader_precompile", true);
 
-   isl_device_init(&screen->isl_dev, &screen->devinfo, false);
+   isl_device_init(&screen->isl_dev, &screen->devinfo);
 
    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
    screen->compiler->shader_debug_log = iris_shader_debug_log;

src/intel/dev/intel_device_info.c

@@ -1397,6 +1397,61 @@ intel_get_aperture_size(int fd, uint64_t *size)
    return ret;
 }
 
+static bool
+has_bit6_swizzle(int fd)
+{
+   struct drm_gem_close close;
+   int ret;
+
+   struct drm_i915_gem_create gem_create = {
+      .size = 4096,
+   };
+
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create)) {
+      unreachable("Failed to create GEM BO");
+      return false;
+   }
+
+   bool swizzled = false;
+
+   /* set_tiling overwrites the input on the error path, so we have to open
+    * code intel_ioctl.
+    */
+   do {
+      struct drm_i915_gem_set_tiling set_tiling = {
+         .handle = gem_create.handle,
+         .tiling_mode = I915_TILING_X,
+         .stride = 512,
+      };
+
+      ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
+   } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
+
+   if (ret != 0) {
+      unreachable("Failed to set BO tiling");
+      goto close_and_return;
+   }
+
+   struct drm_i915_gem_get_tiling get_tiling = {
+      .handle = gem_create.handle,
+   };
+
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) {
+      unreachable("Failed to get BO tiling");
+      goto close_and_return;
+   }
+
+   assert(get_tiling.tiling_mode == I915_TILING_X);
+   swizzled = get_tiling.swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
+
+close_and_return:
+   memset(&close, 0, sizeof(close));
+   close.handle = gem_create.handle;
+   intel_ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
+
+   return swizzled;
+}
+
 static bool
 has_get_tiling(int fd)
 {
@@ -1645,6 +1700,19 @@ intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
    if (devinfo->is_cherryview)
       fixup_chv_device_info(devinfo);
 
+   /* Broadwell PRM says:
+    *
+    *   "Before Gfx8, there was a historical configuration control field to
+    *    swizzle address bit[6] for in X/Y tiling modes. This was set in three
+    *    different places: TILECTL[1:0], ARB_MODE[5:4], and
+    *    DISP_ARB_CTL[14:13].
+    *
+    *    For Gfx8 and subsequent generations, the swizzle fields are all
+    *    reserved, and the CPU's memory controller performs all address
+    *    swizzling modifications."
+    */
+   devinfo->has_bit6_swizzle = devinfo->ver < 8 && has_bit6_swizzle(fd);
+
    intel_get_aperture_size(fd, &devinfo->aperture_bytes);
    devinfo->has_tiling_uapi = has_get_tiling(fd);
 

src/intel/dev/intel_device_info.h

@@ -76,6 +76,7 @@ struct intel_device_info
    bool has_hiz_and_separate_stencil;
    bool must_use_separate_stencil;
    bool has_sample_with_hiz;
+   bool has_bit6_swizzle;
    bool has_llc;
 
    bool has_pln;

src/intel/isl/isl.c

@@ -193,15 +193,14 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
 
 void
 isl_device_init(struct isl_device *dev,
-                const struct intel_device_info *info,
+                const struct intel_device_info *info)
-                bool has_bit6_swizzling)
 {
    /* Gfx8+ don't have bit6 swizzling, ensure callsite is not confused. */
-   assert(!(has_bit6_swizzling && info->ver >= 8));
+   assert(!(info->has_bit6_swizzle && info->ver >= 8));
 
    dev->info = info;
    dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
-   dev->has_bit6_swizzling = has_bit6_swizzling;
+   dev->has_bit6_swizzling = info->has_bit6_swizzle;
 
    /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
     * device properties at buildtime. Verify that the macros with the device

src/intel/isl/isl.h

@@ -1766,8 +1766,7 @@ extern const uint16_t isl_format_name_offsets[];
 
 void
 isl_device_init(struct isl_device *dev,
-                const struct intel_device_info *info,
+                const struct intel_device_info *info);
-                bool has_bit6_swizzling);
 
 isl_sample_count_mask_t ATTRIBUTE_CONST
 isl_device_get_sample_counts(struct isl_device *dev);

src/intel/isl/tests/isl_surf_get_image_offset_test.c

@@ -128,7 +128,7 @@ test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void)
    t_assert(intel_get_device_info_from_pci_id(BDW_GT2_DEVID, &devinfo));
 
    struct isl_device dev;
-   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,
@@ -176,7 +176,7 @@ test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void)
    t_assert(intel_get_device_info_from_pci_id(BDW_GT2_DEVID, &devinfo));
 
    struct isl_device dev;
-   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,
@@ -237,7 +237,7 @@ test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void)
    t_assert(intel_get_device_info_from_pci_id(BDW_GT2_DEVID, &devinfo));
 
    struct isl_device dev;
-   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,

src/intel/vulkan/anv_device.c

@@ -961,21 +961,7 @@ anv_physical_device_try_create(struct anv_instance *instance,
    device->compiler->compact_params = false;
    device->compiler->indirect_ubos_use_sampler = device->info.ver < 12;
 
-   /* Broadwell PRM says:
+   isl_device_init(&device->isl_dev, &device->info);
-    *
-    *   "Before Gfx8, there was a historical configuration control field to
-    *    swizzle address bit[6] for in X/Y tiling modes. This was set in three
-    *    different places: TILECTL[1:0], ARB_MODE[5:4], and
-    *    DISP_ARB_CTL[14:13].
-    *
-    *    For Gfx8 and subsequent generations, the swizzle fields are all
-    *    reserved, and the CPU's memory controller performs all address
-    *    swizzling modifications."
-    */
-   bool swizzled =
-      device->info.ver < 8 && anv_gem_get_bit6_swizzle(fd, I915_TILING_X);
-
-   isl_device_init(&device->isl_dev, &device->info, swizzled);
 
    result = anv_physical_device_init_uuids(device);
    if (result != VK_SUCCESS)

src/intel/vulkan/anv_gem.c

@@ -330,61 +330,6 @@ anv_gem_get_drm_cap(int fd, uint32_t capability)
    return cap.value;
 }
 
-bool
-anv_gem_get_bit6_swizzle(int fd, uint32_t tiling)
-{
-   struct drm_gem_close close;
-   int ret;
-
-   struct drm_i915_gem_create gem_create = {
-      .size = 4096,
-   };
-
-   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create)) {
-      assert(!"Failed to create GEM BO");
-      return false;
-   }
-
-   bool swizzled = false;
-
-   /* set_tiling overwrites the input on the error path, so we have to open
-    * code intel_ioctl.
-    */
-   do {
-      struct drm_i915_gem_set_tiling set_tiling = {
-         .handle = gem_create.handle,
-         .tiling_mode = tiling,
-         .stride = tiling == I915_TILING_X ? 512 : 128,
-      };
-
-      ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
-   } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
-
-   if (ret != 0) {
-      assert(!"Failed to set BO tiling");
-      goto close_and_return;
-   }
-
-   struct drm_i915_gem_get_tiling get_tiling = {
-      .handle = gem_create.handle,
-   };
-
-   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) {
-      assert(!"Failed to get BO tiling");
-      goto close_and_return;
-   }
-
-   swizzled = get_tiling.swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
-
-close_and_return:
-
-   memset(&close, 0, sizeof(close));
-   close.handle = gem_create.handle;
-   intel_ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
-
-   return swizzled;
-}
-
 bool
 anv_gem_has_context_priority(int fd, int priority)
 {

src/intel/vulkan/anv_gem_stubs.c

@@ -143,12 +143,6 @@ anv_gem_get_drm_cap(int fd, uint32_t capability)
    return 0;
 }
 
-bool
-anv_gem_get_bit6_swizzle(int fd, uint32_t tiling)
-{
-   unreachable("Unused");
-}
-
 int
 anv_gem_create_context(struct anv_device *device)
 {

src/intel/vulkan/anv_private.h

@@ -1445,7 +1445,6 @@ int anv_gem_get_context_param(int fd, int context, uint32_t param,
 int anv_gem_get_param(int fd, uint32_t param);
 uint64_t anv_gem_get_drm_cap(int fd, uint32_t capability);
 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
-bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
 int anv_gem_context_get_reset_stats(int fd, int context,
                                     uint32_t *active, uint32_t *pending);
 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);

src/mesa/drivers/dri/i965/brw_context.c

@@ -1011,8 +1011,6 @@ brw_create_context(gl_api api,
    brw->has_hiz = devinfo->has_hiz_and_separate_stencil;
    brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil;
 
-   brw->has_swizzling = screen->hw_has_swizzling;
-
    /* We don't push UBOs on IVB and earlier because the restrictions on
     * 3DSTATE_CONSTANT_* make it really annoying to use push constants
     * without dynamic state base address.

src/mesa/drivers/dri/i965/brw_context.h

@@ -825,7 +825,6 @@ struct brw_context
 
    bool has_hiz;
    bool has_separate_stencil;
-   bool has_swizzling;
 
    bool can_push_ubos;
 

src/mesa/drivers/dri/i965/brw_mipmap_tree.c

@@ -2484,6 +2484,8 @@ brw_miptree_unmap_tiled_memcpy(struct brw_context *brw,
                                unsigned int level,
                                unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    if (map->mode & GL_MAP_WRITE_BIT) {
       unsigned int x1, x2, y1, y2;
       tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
@@ -2493,7 +2495,7 @@ brw_miptree_unmap_tiled_memcpy(struct brw_context *brw,
 
       isl_memcpy_linear_to_tiled(
          x1, x2, y1, y2, dst, map->ptr, mt->surf.row_pitch_B, map->stride,
-         brw->has_swizzling, mt->surf.tiling, ISL_MEMCPY);
+         devinfo->has_bit6_swizzle, mt->surf.tiling, ISL_MEMCPY);
 
       brw_miptree_unmap_raw(mt);
    }
@@ -2567,6 +2569,8 @@ brw_miptree_map_tiled_memcpy(struct brw_context *brw,
                              struct brw_miptree_map *map,
                              unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    brw_miptree_access_raw(brw, mt, level, slice,
                           map->mode & GL_MAP_WRITE_BIT);
 
@@ -2595,7 +2599,7 @@ brw_miptree_map_tiled_memcpy(struct brw_context *brw,
 
       isl_memcpy_tiled_to_linear(
          x1, x2, y1, y2, map->ptr, src, map->stride,
-         mt->surf.row_pitch_B, brw->has_swizzling, mt->surf.tiling,
+         mt->surf.row_pitch_B, devinfo->has_bit6_swizzle, mt->surf.tiling,
          copy_type);
 
       brw_miptree_unmap_raw(mt);
@@ -2748,6 +2752,8 @@ brw_miptree_unmap_s8(struct brw_context *brw,
                      unsigned int level,
                      unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    if (map->mode & GL_MAP_WRITE_BIT) {
       unsigned int image_x, image_y;
       uint8_t *untiled_s8_map = map->ptr;
@@ -2760,7 +2766,7 @@ brw_miptree_unmap_s8(struct brw_context *brw,
             ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
                                              image_x + x + map->x,
                                              image_y + y + map->y,
-                                             brw->has_swizzling);
+                                             devinfo->has_bit6_swizzle);
             tiled_s8_map[offset] = untiled_s8_map[y * map->w + x];
          }
       }
@@ -2777,6 +2783,8 @@ brw_miptree_map_s8(struct brw_context *brw,
                    struct brw_miptree_map *map,
                    unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
+
    map->stride = map->w;
    map->buffer = map->ptr = malloc(map->stride * map->h);
    if (!map->buffer)
@@ -2802,7 +2810,7 @@ brw_miptree_map_s8(struct brw_context *brw,
             ptrdiff_t offset = brw_offset_S8(mt->surf.row_pitch_B,
                                              x + image_x + map->x,
                                              y + image_y + map->y,
-                                             brw->has_swizzling);
+                                             devinfo->has_bit6_swizzle);
             untiled_s8_map[y * map->w + x] = tiled_s8_map[offset];
          }
       }
@@ -2839,6 +2847,7 @@ brw_miptree_unmap_depthstencil(struct brw_context *brw,
                                unsigned int level,
                                unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
    struct brw_mipmap_tree *z_mt = mt;
    struct brw_mipmap_tree *s_mt = mt->stencil_mt;
    bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
@@ -2860,7 +2869,7 @@ brw_miptree_unmap_depthstencil(struct brw_context *brw,
             ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
                                                x + s_image_x + map->x,
                                                y + s_image_y + map->y,
-                                               brw->has_swizzling);
+                                               devinfo->has_bit6_swizzle);
             ptrdiff_t z_offset = ((y + z_image_y + map->y) *
                                   (z_mt->surf.row_pitch_B / 4) +
                                   (x + z_image_x + map->x));
@@ -2897,6 +2906,7 @@ brw_miptree_map_depthstencil(struct brw_context *brw,
                              struct brw_miptree_map *map,
                              unsigned int level, unsigned int slice)
 {
+   const struct intel_device_info *devinfo = &brw->screen->devinfo;
    struct brw_mipmap_tree *z_mt = mt;
    struct brw_mipmap_tree *s_mt = mt->stencil_mt;
    bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
@@ -2935,7 +2945,7 @@ brw_miptree_map_depthstencil(struct brw_context *brw,
             ptrdiff_t s_offset = brw_offset_S8(s_mt->surf.row_pitch_B,
                                                  map_x + s_image_x,
                                                  map_y + s_image_y,
-                                                 brw->has_swizzling);
+                                                 devinfo->has_bit6_swizzle);
             ptrdiff_t z_offset = ((map_y + z_image_y) *
                                   (z_mt->surf.row_pitch_B / 4) +
                                   (map_x + z_image_x));

src/mesa/drivers/dri/i965/brw_pixel_read.c

@@ -143,7 +143,7 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    /* Since we are going to read raw data to the miptree, we need to resolve
@@ -204,7 +204,7 @@ brw_readpixels_tiled_memcpy(struct gl_context *ctx,
       pixels,
       map + irb->mt->offset,
       dst_pitch, irb->mt->surf.row_pitch_B,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       irb->mt->surf.tiling,
       copy_type
    );

src/mesa/drivers/dri/i965/brw_screen.c

@@ -1915,37 +1915,6 @@ brw_init_bufmgr(struct brw_screen *screen)
    return true;
 }
 
-static bool
-brw_detect_swizzling(struct brw_screen *screen)
-{
-   /* Broadwell PRM says:
-    *
-    *   "Before Gfx8, there was a historical configuration control field to
-    *    swizzle address bit[6] for in X/Y tiling modes. This was set in three
-    *    different places: TILECTL[1:0], ARB_MODE[5:4], and
-    *    DISP_ARB_CTL[14:13].
-    *
-    *    For Gfx8 and subsequent generations, the swizzle fields are all
-    *    reserved, and the CPU's memory controller performs all address
-    *    swizzling modifications."
-    */
-   if (screen->devinfo.ver >= 8)
-      return false;
-
-   uint32_t tiling = I915_TILING_X;
-   uint32_t swizzle_mode = 0;
-   struct brw_bo *buffer =
-      brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
-                         BRW_MEMZONE_OTHER, tiling, 512, 0);
-   if (buffer == NULL)
-      return false;
-
-   brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
-   brw_bo_unreference(buffer);
-
-   return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
-}
-
 static int
 brw_detect_timestamp(struct brw_screen *screen)
 {
@@ -2603,11 +2572,9 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
 
    screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4;
 
-   screen->hw_has_swizzling = brw_detect_swizzling(screen);
    screen->hw_has_timestamp = brw_detect_timestamp(screen);
 
-   isl_device_init(&screen->isl_dev, &screen->devinfo,
+   isl_device_init(&screen->isl_dev, &screen->devinfo);
-                   screen->hw_has_swizzling);
 
    /* Gfx7-7.5 kernel requirements / command parser saga:
     *

src/mesa/drivers/dri/i965/brw_screen.h

@@ -59,7 +59,6 @@ struct brw_screen
    /** DRM fd associated with this screen. Not owned by this object. Do not close. */
    int fd;
 
-   bool hw_has_swizzling;
    bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */
 
    int hw_has_timestamp;

src/mesa/drivers/dri/i965/brw_tex_image.c

@@ -246,7 +246,7 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    int level = texImage->Level + texImage->TexObject->Attrib.MinLevel;
@@ -297,7 +297,7 @@ brw_texsubimage_tiled_memcpy(struct gl_context * ctx,
       map,
       pixels,
       image->mt->surf.row_pitch_B, src_pitch,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       image->mt->surf.tiling,
       copy_type
    );
@@ -798,7 +798,7 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
     * parts of the memory aren't swizzled at all. Userspace just can't handle
     * that.
     */
-   if (devinfo->ver < 5 && brw->has_swizzling)
+   if (devinfo->ver < 5 && devinfo->has_bit6_swizzle)
       return false;
 
    int level = texImage->Level + texImage->TexObject->Attrib.MinLevel;
@@ -846,7 +846,7 @@ brw_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
       pixels,
       map,
       dst_pitch, image->mt->surf.row_pitch_B,
-      brw->has_swizzling,
+      devinfo->has_bit6_swizzle,
       image->mt->surf.tiling,
       copy_type
    );