ac,radv,radeonsi: introduce a helper to build a FMASK descriptor
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29259>
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Samuel Pitoiset
committed by
Marge Bot
Marge Bot
parent
e1b4b399ce
commit
95122a1cf7
@@ -6,6 +6,7 @@
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*/
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#include "ac_descriptors.h"
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#include "ac_surface.h"
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#include "sid.h"
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@@ -62,3 +63,241 @@ ac_build_sampler_descriptor(const enum amd_gfx_level gfx_level, const struct ac_
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desc[3] |= S_008F3C_BORDER_COLOR_PTR_GFX6(state->border_color_ptr);
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}
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}
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static void
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ac_build_gfx6_fmask_descriptor(const enum amd_gfx_level gfx_level, const struct ac_fmask_state *state, uint32_t desc[8])
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{
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const struct radeon_surf *surf = state->surf;
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const uint64_t va = state->va + surf->fmask_offset;
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uint32_t data_format, num_format;
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#define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
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if (gfx_level == GFX9) {
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
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switch (FMASK(state->num_samples, state->num_storage_samples)) {
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case FMASK(2, 1):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_1;
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break;
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case FMASK(2, 2):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
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break;
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case FMASK(4, 1):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_1;
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break;
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case FMASK(4, 2):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_2;
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break;
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case FMASK(4, 4):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
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break;
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case FMASK(8, 1):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_8_1;
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break;
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case FMASK(8, 2):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_8_2;
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break;
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case FMASK(8, 4):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_4;
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break;
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case FMASK(8, 8):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
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break;
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case FMASK(16, 1):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_16_1;
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break;
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case FMASK(16, 2):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_16_2;
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break;
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case FMASK(16, 4):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_4;
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break;
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case FMASK(16, 8):
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num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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} else {
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switch (FMASK(state->num_samples, state->num_storage_samples)) {
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case FMASK(2, 1):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
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break;
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case FMASK(2, 2):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
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break;
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case FMASK(4, 1):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
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break;
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case FMASK(4, 2):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
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break;
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case FMASK(4, 4):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
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break;
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case FMASK(8, 1):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
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break;
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case FMASK(8, 2):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
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break;
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case FMASK(8, 4):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
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break;
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case FMASK(8, 8):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
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break;
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case FMASK(16, 1):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
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break;
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case FMASK(16, 2):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
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break;
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case FMASK(16, 4):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
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break;
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case FMASK(16, 8):
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data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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num_format = V_008F14_IMG_NUM_FORMAT_UINT;
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}
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#undef FMASK
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desc[0] = (va >> 8) | surf->fmask_tile_swizzle;
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desc[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
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S_008F14_DATA_FORMAT(data_format) |
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S_008F14_NUM_FORMAT(num_format);
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desc[2] = S_008F18_WIDTH(state->width - 1) |
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S_008F18_HEIGHT(state->height - 1);
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desc[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_008F1C_TYPE(state->type);
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desc[4] = 0;
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desc[5] = S_008F24_BASE_ARRAY(state->first_layer);
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desc[6] = 0;
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desc[7] = 0;
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if (gfx_level == GFX9) {
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desc[3] |= S_008F1C_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode);
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desc[4] |= S_008F20_DEPTH(state->last_layer) |
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S_008F20_PITCH(surf->u.gfx9.color.fmask_epitch);
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desc[5] |= S_008F24_META_PIPE_ALIGNED(1) |
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S_008F24_META_RB_ALIGNED(1);
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if (state->tc_compat_cmask) {
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const uint64_t cmask_va = state->va + surf->cmask_offset;
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desc[5] |= S_008F24_META_DATA_ADDRESS(cmask_va >> 40);
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desc[6] |= S_008F28_COMPRESSION_EN(1);
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desc[7] |= cmask_va >> 8;
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}
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} else {
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desc[3] |= S_008F1C_TILING_INDEX(surf->u.legacy.color.fmask.tiling_index);
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desc[4] |= S_008F20_DEPTH(state->depth - 1) |
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S_008F20_PITCH(surf->u.legacy.color.fmask.pitch_in_pixels - 1);
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desc[5] |= S_008F24_LAST_ARRAY(state->last_layer);
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if (state->tc_compat_cmask) {
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const uint64_t cmask_va = state->va + surf->cmask_offset;
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desc[6] |= S_008F28_COMPRESSION_EN(1);
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desc[7] |= cmask_va >> 8;
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}
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}
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}
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static void
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ac_build_gfx10_fmask_descriptor(const enum amd_gfx_level gfx_level, const struct ac_fmask_state *state, uint32_t desc[8])
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{
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const struct radeon_surf *surf = state->surf;
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const uint64_t va = state->va + surf->fmask_offset;
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uint32_t format;
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#define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
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switch (FMASK(state->num_samples, state->num_storage_samples)) {
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case FMASK(2, 1):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S2_F1;
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break;
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case FMASK(2, 2):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S2_F2;
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break;
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case FMASK(4, 1):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F1;
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break;
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case FMASK(4, 2):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F2;
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break;
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case FMASK(4, 4):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F4;
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break;
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case FMASK(8, 1):
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format = V_008F0C_GFX10_FORMAT_FMASK8_S8_F1;
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break;
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case FMASK(8, 2):
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format = V_008F0C_GFX10_FORMAT_FMASK16_S8_F2;
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break;
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case FMASK(8, 4):
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format = V_008F0C_GFX10_FORMAT_FMASK32_S8_F4;
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break;
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case FMASK(8, 8):
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format = V_008F0C_GFX10_FORMAT_FMASK32_S8_F8;
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break;
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case FMASK(16, 1):
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format = V_008F0C_GFX10_FORMAT_FMASK16_S16_F1;
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break;
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case FMASK(16, 2):
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format = V_008F0C_GFX10_FORMAT_FMASK32_S16_F2;
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break;
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case FMASK(16, 4):
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format = V_008F0C_GFX10_FORMAT_FMASK64_S16_F4;
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break;
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case FMASK(16, 8):
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format = V_008F0C_GFX10_FORMAT_FMASK64_S16_F8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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#undef FMASK
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desc[0] = (va >> 8) | surf->fmask_tile_swizzle;
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desc[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
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S_00A004_FORMAT_GFX10(format) |
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S_00A004_WIDTH_LO(state->width - 1);
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desc[2] = S_00A008_WIDTH_HI((state->width - 1) >> 2) |
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S_00A008_HEIGHT(state->height - 1) |
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S_00A008_RESOURCE_LEVEL(1);
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desc[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_00A00C_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
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S_00A00C_TYPE(state->type);
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desc[4] = S_00A010_DEPTH_GFX10(state->last_layer) | S_00A010_BASE_ARRAY(state->first_layer);
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desc[5] = 0;
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desc[6] = S_00A018_META_PIPE_ALIGNED(1);
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desc[7] = 0;
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if (state->tc_compat_cmask) {
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uint64_t cmask_va = state->va + surf->cmask_offset;
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desc[6] |= S_00A018_COMPRESSION_EN(1);
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desc[6] |= S_00A018_META_DATA_ADDRESS_LO(cmask_va >> 8);
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desc[7] |= cmask_va >> 16;
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}
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}
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void
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ac_build_fmask_descriptor(const enum amd_gfx_level gfx_level, const struct ac_fmask_state *state, uint32_t desc[8])
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{
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assert(gfx_level < GFX11);
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if (gfx_level >= GFX10) {
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ac_build_gfx10_fmask_descriptor(gfx_level, state, desc);
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} else {
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ac_build_gfx6_fmask_descriptor(gfx_level, state, desc);
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}
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}
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