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radeon/llvm: Use a custom inserter to lower STORE_OUTPUT

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This commit is contained in:
Tom Stellard
2012-05-08 10:27:30 -04:00
parent 4226433625
commit 94e797d0fa
4 changed files with 23 additions and 34 deletions
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7
src/gallium/drivers/radeon/AMDGPUInstructions.td
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@@ -55,13 +55,6 @@ let isCodeGenOnly = 1 in {
"RESERVE_REG $dst, $src",
[(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]
>;
def STORE_OUTPUT: AMDGPUShaderInst <
(outs GPRF32:$dst),
(ins GPRF32:$src0, i32imm:$src1),
"STORE_OUTPUT $dst, $src0, $src1",
[(set GPRF32:$dst, (int_AMDGPU_store_output GPRF32:$src0, imm:$src1))]
>;
}
/* Generic helper patterns for intrinsics */

16
src/gallium/drivers/radeon/R600ISelLowering.cpp
View File

@@ -96,6 +96,22 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDIL::STORE_OUTPUT:
{
MachineBasicBlock::iterator I = *MI;
int64_t OutputIndex = MI->getOperand(2).getImm();
unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY), OutputReg)
.addOperand(MI->getOperand(1));
MRI.replaceRegWith(MI->getOperand(0).getReg(), OutputReg);
if (!MRI.isLiveOut(OutputReg)) {
MRI.addLiveOut(OutputReg);
}
MI->eraseFromParent();
break;
}
}
return BB;
}

7
src/gallium/drivers/radeon/R600Instructions.td
View File

@@ -998,6 +998,13 @@ def LOAD_INPUT : AMDGPUShaderInst <
[(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
>;
def STORE_OUTPUT: AMDGPUShaderInst <
(outs R600_Reg32:$dst),
(ins R600_Reg32:$src0, i32imm:$src1),
"STORE_OUTPUT $dst, $src0, $src1",
[(set R600_Reg32:$dst, (int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1))]
>;
} // End usesCustomInserter = 1, isPseudo = 1
} // End isCodeGenOnly = 1

27
src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
View File

@@ -31,8 +31,6 @@ namespace {
void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
bool lowerSTORE_OUTPUT(MachineInstr & MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);
public:
R600LowerShaderInstructionsPass(TargetMachine &tm) :
@@ -79,10 +77,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
deleteInstr = true;
break;
case AMDIL::STORE_OUTPUT:
deleteInstr = lowerSTORE_OUTPUT(MI, MBB, I);
break;
}
++I;
@@ -95,24 +89,3 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
return false;
}
bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
{
MachineOperand &valueOp = MI.getOperand(1);
MachineOperand &indexOp = MI.getOperand(2);
unsigned valueReg = valueOp.getReg();
int64_t outputIndex = indexOp.getImm();
const TargetRegisterClass * outputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
unsigned newRegister = outputClass->getRegister(outputIndex);
BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::COPY),
newRegister)
.addReg(valueReg);
if (!MRI->isLiveOut(newRegister))
MRI->addLiveOut(newRegister);
return true;
}