freedreno/a6xx: Move tess-bo emit
Move this to where the rest of the hs/ds params are emit, because for a7xx with load_shader_consts_via_preamble we'll need this all to be a single UBO. So we won't be able to piecemeal upload consts. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31534>
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@@ -107,7 +107,6 @@ struct fd_ringbuffer *
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fd6_build_tess_consts(struct fd6_emit *emit)
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{
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struct fd_context *ctx = emit->ctx;
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struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
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ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
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@@ -126,10 +125,22 @@ fd6_build_tess_consts(struct fd6_emit *emit)
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emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
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if (emit->hs) {
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uint32_t hs_params[4] = {
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struct fd_bo *tess_bo = ctx->screen->tess_bo;
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int64_t tess_factor_iova = fd_bo_get_iova(tess_bo);
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int64_t tess_param_iova = tess_factor_iova + FD6_TESS_FACTOR_SIZE;
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fd_ringbuffer_attach_bo(constobj, tess_bo);
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uint32_t hs_params[8] = {
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emit->vs->output_size * num_vertices * 4, /* vs primitive stride */
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emit->vs->output_size * 4, /* vs vertex stride */
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emit->hs->output_size, ctx->patch_vertices};
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emit->hs->output_size,
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ctx->patch_vertices,
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tess_param_iova,
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tess_param_iova >> 32,
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tess_factor_iova,
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tess_factor_iova >> 32,
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};
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emit_stage_tess_consts(constobj, emit->hs, hs_params,
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ARRAY_SIZE(hs_params));
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@@ -137,11 +148,16 @@ fd6_build_tess_consts(struct fd6_emit *emit)
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if (emit->gs)
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num_vertices = emit->gs->gs.vertices_in;
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uint32_t ds_params[4] = {
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uint32_t ds_params[8] = {
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emit->ds->output_size * num_vertices * 4, /* ds primitive stride */
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emit->ds->output_size * 4, /* ds vertex stride */
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emit->hs->output_size, /* hs vertex stride (dwords) */
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emit->hs->tess.tcs_vertices_out};
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emit->hs->output_size, /* hs vertex stride (dwords) */
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emit->hs->tess.tcs_vertices_out,
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tess_param_iova,
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tess_param_iova >> 32,
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tess_factor_iova,
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tess_factor_iova >> 32,
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};
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emit_stage_tess_consts(constobj, emit->ds, ds_params,
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ARRAY_SIZE(ds_params));
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@@ -466,31 +466,6 @@ next_regid(uint32_t reg, uint32_t increment)
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return regid(63, 0);
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}
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static void
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fd6_emit_tess_bos(struct fd_screen *screen, struct fd_ringbuffer *ring,
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const struct ir3_shader_variant *s) assert_dt
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{
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const struct ir3_const_state *const_state = ir3_const_state(s);
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const unsigned regid = const_state->offsets.primitive_param + 1;
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uint32_t dwords = 8;
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if (regid >= s->constlen)
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return;
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fd_ringbuffer_attach_bo(ring, screen->tess_bo);
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OUT_PKT7(ring, fd6_stage2opcode(s->type), 7);
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OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
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CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
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OUT_RING(ring, 0);
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OUT_RING(ring, 0);
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OUT_RELOC(ring, screen->tess_bo, FD6_TESS_FACTOR_SIZE, 0, 0);
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OUT_RELOC(ring, screen->tess_bo, 0, 0, 0);
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}
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static enum a6xx_tess_output
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primitive_to_tess(enum mesa_prim primitive)
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{
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@@ -1191,11 +1166,6 @@ setup_stateobj(struct fd_ringbuffer *ring, const struct program_builder *b)
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emit_fs_inputs<CHIP>(ring, b);
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emit_fs_outputs(ring, b);
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if (b->hs) {
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fd6_emit_tess_bos(b->ctx->screen, ring, b->hs);
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fd6_emit_tess_bos(b->ctx->screen, ring, b->ds);
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}
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if (b->hs) {
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uint32_t patch_control_points = b->key->patch_vertices;
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