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nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO

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Those varyings shouldn't flag patch_inputs_read/patch_outputs_written.

Fixes: 10be706778 - nir: gather indirect info from lowered IO intrinsics

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26275>
(cherry picked from commit 7a9b73fcb8)
This commit is contained in:
Marek Olšák
2023-11-13 00:16:24 -05:00
committed by Eric Engestrom
parent 3ed7b95a55
commit 94ad18d1e7
3 changed files with 14 additions and 5 deletions
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2
.pick_status.json
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@@ -184,7 +184,7 @@
"description": "nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO", "description": "nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO",
"nominated": true, "nominated": true,
"nomination_type": 1, "nomination_type": 1,
"resolution": 0, "resolution": 1,
"main_sha": null, "main_sha": null,
"because_sha": "10be706778bd670197a66765c550cbb3a0cfda6d", "because_sha": "10be706778bd670197a66765c550cbb3a0cfda6d",
"notes": null "notes": null

15
src/compiler/nir/nir_gather_info.c
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@@ -410,10 +410,16 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
{ {
uint64_t slot_mask = 0; uint64_t slot_mask = 0;
uint16_t slot_mask_16bit = 0; uint16_t slot_mask_16bit = 0;
bool is_patch_special = false;
if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) { if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
nir_io_semantics semantics = nir_intrinsic_io_semantics(instr); nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
is_patch_special = semantics.location == VARYING_SLOT_TESS_LEVEL_INNER ||
semantics.location == VARYING_SLOT_TESS_LEVEL_OUTER ||
semantics.location == VARYING_SLOT_BOUNDING_BOX0 ||
semantics.location == VARYING_SLOT_BOUNDING_BOX1;
if (semantics.location >= VARYING_SLOT_PATCH0 && if (semantics.location >= VARYING_SLOT_PATCH0 &&
semantics.location <= VARYING_SLOT_PATCH31) { semantics.location <= VARYING_SLOT_PATCH31) {
/* Generic per-patch I/O. */ /* Generic per-patch I/O. */
@@ -516,7 +522,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_load_input_vertex: case nir_intrinsic_load_input_vertex:
case nir_intrinsic_load_interpolated_input: case nir_intrinsic_load_interpolated_input:
if (shader->info.stage == MESA_SHADER_TESS_EVAL && if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
instr->intrinsic == nir_intrinsic_load_input) { instr->intrinsic == nir_intrinsic_load_input &&
!is_patch_special) {
shader->info.patch_inputs_read |= slot_mask; shader->info.patch_inputs_read |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr))) if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_inputs_read_indirectly |= slot_mask; shader->info.patch_inputs_read_indirectly |= slot_mask;
@@ -541,7 +548,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_load_per_vertex_output: case nir_intrinsic_load_per_vertex_output:
case nir_intrinsic_load_per_primitive_output: case nir_intrinsic_load_per_primitive_output:
if (shader->info.stage == MESA_SHADER_TESS_CTRL && if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_load_output) { instr->intrinsic == nir_intrinsic_load_output &&
!is_patch_special) {
shader->info.patch_outputs_read |= slot_mask; shader->info.patch_outputs_read |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr))) if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask; shader->info.patch_outputs_accessed_indirectly |= slot_mask;
@@ -575,7 +583,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_store_per_vertex_output: case nir_intrinsic_store_per_vertex_output:
case nir_intrinsic_store_per_primitive_output: case nir_intrinsic_store_per_primitive_output:
if (shader->info.stage == MESA_SHADER_TESS_CTRL && if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_store_output) { instr->intrinsic == nir_intrinsic_store_output &&
!is_patch_special) {
shader->info.patch_outputs_written |= slot_mask; shader->info.patch_outputs_written |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr))) if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask; shader->info.patch_outputs_accessed_indirectly |= slot_mask;

2
src/gallium/drivers/radeonsi/si_shader_info.c
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@@ -617,7 +617,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
} }
/* tess factors are loaded as input instead of system value */ /* tess factors are loaded as input instead of system value */
info->reads_tess_factors = nir->info.patch_inputs_read & info->reads_tess_factors = nir->info.inputs_read &
(BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) | (BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) |
BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER)); BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER));