ir3: Better assemble/disassemble stc
Add in the type, even though it turns out to not be that useful. Add in support for assembling it. Add some notes based on computerator experiments. And add support for the indirect a1.x mode that's needed for storing c64.x and later. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
This commit is contained in:
Connor Abbott
@@ -394,6 +394,7 @@ static const struct opc_info {
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OPC(6, OPC_GETSPID, getspid),
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OPC(6, OPC_GETWID, getwid),
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OPC(6, OPC_GETFIBERID, getfiberid),
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OPC(6, OPC_STC, stc),
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OPC(6, OPC_SPILL_MACRO, spill.macro),
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OPC(6, OPC_RELOAD_MACRO, reload.macro),
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@@ -374,6 +374,7 @@ static int parse_reg(const char *str)
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"getspid" return TOKEN(T_OP_GETSPID);
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"getwid" return TOKEN(T_OP_GETWID);
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"getfiberid" return TOKEN(T_OP_GETFIBERID);
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"stc" return TOKEN(T_OP_STC);
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/* category 7: */
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"bar" return TOKEN(T_OP_BAR);
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@@ -613,6 +613,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
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%token <tok> T_OP_GETSPID
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%token <tok> T_OP_GETWID
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%token <tok> T_OP_GETFIBERID
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%token <tok> T_OP_STC
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/* category 7: */
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%token <tok> T_OP_BAR
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@@ -1235,6 +1236,12 @@ cat6_bindless_ldc: cat6_bindless_ldc_opc '.' T_OFFSET '.' cat6_immed '.' cat6_bi
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swap(instr->srcs[0], instr->srcs[1]);
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}
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stc_dst: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
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| T_A1 { new_src(0, IR3_REG_IMMED)->iim_val = 0; instr->flags |= IR3_INSTR_A1EN; }
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| T_A1 '+' integer { new_src(0, IR3_REG_IMMED)->iim_val = $3; instr->flags |= IR3_INSTR_A1EN; }
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cat6_stc: T_OP_STC { new_instr(OPC_STC); } cat6_type 'c' '[' stc_dst ']' ',' src_reg ',' cat6_immed
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cat6_todo: T_OP_G2L { new_instr(OPC_G2L); }
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| T_OP_L2G { new_instr(OPC_L2G); }
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| T_OP_RESFMT { new_instr(OPC_RESFMT); }
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@@ -1249,6 +1256,7 @@ cat6_instr: cat6_load
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| cat6_id
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| cat6_bindless_ldc
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| cat6_bindless_ibo
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| cat6_stc
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| cat6_todo
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cat7_scope: '.' 'w' { instr->cat7.w = true; }
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@@ -346,6 +346,10 @@ validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr)
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case OPC_GETWID:
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validate_reg_size(ctx, instr->dsts[0], instr->cat6.type);
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break;
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case OPC_STC:
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validate_reg_size(ctx, instr->srcs[0], instr->cat6.type);
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validate_assert(ctx, !(instr->srcs[1]->flags & IR3_REG_HALF));
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break;
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default:
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validate_reg_size(ctx, instr->dsts[0], instr->cat6.type);
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validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF));
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@@ -227,9 +227,13 @@ static const struct test {
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INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
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/* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
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INSTR_6XX(c7020020_01800000, "stc c[32], r0.x, 1", .parse_fail=true),
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INSTR_6XX(c7020020_01800000, "stc.f32 c[32], r0.x, 1"), /* stc c[32], r0.x, 1 */
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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INSTR_6XX(c7060020_03800000, "stc c[32], r0.x, 3", .parse_fail=true),
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INSTR_6XX(c7060020_03800000, "stc.u32 c[32], r0.x, 3"), /* stc c[32], r0.x, 3 */
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/* custom */
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INSTR_6XX(c7060100_03800000, "stc.u32 c[a1.x], r0.x, 3"), /* stc c[a1.x], r0.x, 3 */
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INSTR_6XX(c7060120_03800000, "stc.u32 c[a1.x+32], r0.x, 3"), /* stc c[a1.x+32], r0.x, 3 */
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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INSTR_6XX(c0260200_03676100, "stib.b.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
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@@ -308,6 +308,17 @@ __cat3_src_case(struct encode_state *s, struct ir3_register *reg)
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}
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}
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typedef enum {
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STC_DST_IMM,
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STC_DST_A1
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} stc_dst_t;
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static inline stc_dst_t
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__stc_dst_case(struct encode_state *s, struct ir3_instruction *instr)
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{
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return (instr->flags & IR3_INSTR_A1EN) ? STC_DST_A1 : STC_DST_IMM;
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}
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#include "encode.h"
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@@ -325,21 +325,55 @@ SOFTWARE.
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<pattern low="54" high="58">01011</pattern> <!-- OPC -->
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</bitset>
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<bitset name="#stc-dst-imm" extends="#stc-dst">
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<display>
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{OFFSET}
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</display>
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<field name="OFFSET" low="0" high="7" type="uint"/>
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<pattern pos="8">0</pattern>
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</bitset>
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<bitset name="#stc-dst-a1" extends="#stc-dst">
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<display>
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a1.x{OFFSET}
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</display>
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<field name="OFFSET" low="0" high="7" type="uoffset"/>
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<pattern pos="8">1</pattern>
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</bitset>
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<bitset name="#stc-dst" size="9">
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<doc>
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Encoding for stc destination which can be constant or have an
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offset of a1.x.
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</doc>
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<encode type="struct ir3_instruction *" case-prefix="">
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<map name="OFFSET">extract_reg_uim(src->srcs[0])</map>
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</encode>
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</bitset>
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<bitset name="stc" extends="#instruction-cat6-a3xx">
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<doc>
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STore Const - used for shader prolog (between shps and shpe)
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to store "uniform folded" values into CONST file
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NOTE: TYPE field actually seems to be set to different
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values (ie f32 vs u32), but I *think* it does not matter.
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(There is SP_MODE_CONTROL.CONSTANT_DEMOTION_ENABLE, but
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I think float results are already converted to 32b)
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values (ie f32 vs u32), but it seems that only the size (16b vs
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32b) matters. Setting a 16-bit type (f16, u16, or s16) doesn't
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cause any promotion to 32-bit, it causes the 16-bit sources to
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be stored one after the other starting with the low half of the
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constant. So e.g. "stc.f16 c[1], hr0.x, 1" copies hr0.x to the
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bottom half of c0.y. There seems to be no way to set just the
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upper half. In any case, the blob seems to only use the 32-bit
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versions.
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NOTE: this could be the "old" encoding, although it
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would conflict with stgb from earlier gens
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The blob disassembly doesn't include the type, but we still
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display it so that we can preserve the different values the blob
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sets when round-tripping.
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NOTE: this conflicts with stgb from earlier gens
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</doc>
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<display>
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{SY}{JP}{NAME} c[{DST}], {SRC}, {SIZE}
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{SY}{JP}{NAME}.{TYPE} c[{DST}], {SRC}, {SIZE}
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</display>
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<gen min="600"/>
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<pattern pos="0" >x</pattern>
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@@ -348,13 +382,14 @@ SOFTWARE.
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<pattern pos="23" >1</pattern>
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<field low="24" high="26" name="SIZE" type="uint"/>
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<pattern low="27" high="31">xxxxx</pattern>
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<field low="32" high="39" name="DST" type="uint"/>
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<pattern low="40" high="48">xxxxxxxxx</pattern>
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<field low="32" high="40" name="DST" type="#stc-dst"/>
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<pattern low="41" high="48">xxxxxxxx</pattern>
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<pattern low="52" high="53">xx</pattern>
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<pattern low="54" high="58">11100</pattern> <!-- OPC -->
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<encode>
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<map name="DST">extract_reg_uim(src->srcs[0])</map>
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<map name="DST">src</map>
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<map name="SRC">src->srcs[1]</map>
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<map name="SIZE">src->cat6.iim_val</map>
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</encode>
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</bitset>
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