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Revert "radv,aco: allow unaligned LDS access on GFX9+"

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This reverts commit 1a0b0e8460.

The bounds checking behaviour of ds_read_b64, ds_read_b96 and ds_read_b128
make this feature very difficult to use safely.

This fixes a blocking artifact in Hitman 2. Previously, it contained:
ds_read_b64(local_invocation_index() * 4 - 4)
For local_invocation_index()=0, the second dword would be considered
out-of-bounds, even though it's at offset 0.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9332>
This commit is contained in:
Rhys Perry
2021-03-01 10:43:01 +00:00
committed by Marge Bot
parent acbd4881c2
commit 941739619e
4 changed files with 12 additions and 25 deletions
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8
src/amd/vulkan/radv_pipeline.c
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@@ -3053,9 +3053,6 @@ mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
nir_intrinsic_instr *low, nir_intrinsic_instr *high,
void *data)
{
struct radv_device *device = data;
enum chip_class chip = device->physical_device->rad_info.chip_class;
if (num_components > 4)
return false;
@@ -3084,9 +3081,9 @@ mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
FALLTHROUGH;
case nir_intrinsic_load_shared:
case nir_intrinsic_store_shared:
if (chip < GFX9 && bit_size * num_components == 96) /* 96 bit loads require 128 bit alignment on GFX6-8 and are split otherwise */
if (bit_size * num_components == 96) /* 96 bit loads require 128 bit alignment and are split otherwise */
return align % 16 == 0;
else if (chip < GFX9 && bit_size * num_components == 128) /* 128 bit loads require 64 bit alignment on GFX6-8 and are split otherwise */
else if (bit_size * num_components == 128) /* 128 bit loads require 64 bit alignment and are split otherwise */
return align % 8 == 0;
else
return align % (bit_size == 8 ? 2 : 4) == 0;
@@ -3335,7 +3332,6 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
nir_var_mem_push_const | nir_var_mem_shared |
nir_var_mem_global,
.callback = mem_vectorize_callback,
.cb_data = device,
.robust_modes = 0,
};