From 938f79ed8266f963968bc1da4dd407f19b84794e Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 10 Apr 2025 09:24:10 +0300 Subject: [PATCH] anv: update Wa_1607156449 to use WA infrastructure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: José Roberto de Souza Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index f5bd30a45b7..c5e4252201f 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2467,11 +2467,12 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, /* XXX - insert all workarounds and GFX specific things below. */ - /* Wa_14014966230: For COMPUTE Workload - Any PIPE_CONTROL command with - * POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL - * with CS_STALL Bit set (with No POST_SYNC ENABLED) +#if INTEL_WA_1607156449_GFX_VER + /* Wa_1607156449: For COMPUTE Workload - Any PIPE_CONTROL command with + * POST_SYNC Operation Enabled MUST be preceded by a PIPE_CONTROL with + * CS_STALL Bit set (with No POST_SYNC ENABLED) */ - if (intel_device_info_is_adln(devinfo) && + if (intel_needs_workaround(devinfo, 1607156449) && current_pipeline == GPGPU && post_sync_op != NoWrite) { anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) { @@ -2479,6 +2480,7 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, anv_debug_dump_pc(pipe, "Wa_14014966230"); }; } +#endif /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for * PIPE_CONTROL, Flush Types: