iris: expand pre-hiz data cache flush to gfx >= 125

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27132>
This commit is contained in:
Tapani Pälli
2024-01-18 07:20:24 +02:00
committed by Marge Bot
parent 7481d61a5d
commit 93706d5c2f

View File

@@ -703,7 +703,7 @@ iris_hiz_exec(struct iris_context *ice,
/* A data cache flush is not suggested by HW docs, but we found it to fix
* a number of failures.
*/
unsigned wa_flush = intel_device_info_is_dg2(batch->screen->devinfo) &&
unsigned wa_flush = devinfo->verx10 >= 125 &&
res->aux.usage == ISL_AUX_USAGE_HIZ_CCS ?
PIPE_CONTROL_DATA_CACHE_FLUSH : 0;