From 92e5eee39e51a5b89e36f68bcc3d6e405ec07e6e Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 25 Apr 2022 08:40:28 +0200 Subject: [PATCH] radv: use correct push constants range for internal operations Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_meta_bufimage.c | 18 +++++++++--------- src/amd/vulkan/radv_meta_resolve_cs.c | 2 +- src/amd/vulkan/radv_meta_resolve_fs.c | 2 +- src/amd/vulkan/radv_query.c | 18 +++++++++--------- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 2d0b99e7ce8..63307e0b2ec 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -53,7 +53,7 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *global_id = get_global_ids(&b, is_3d ? 3 : 2); nir_ssa_def *offset = - nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = 16); + nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = is_3d ? 12 : 8); nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16); nir_ssa_def *img_coord = nir_iadd(&b, global_id, offset); @@ -234,7 +234,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *global_id = get_global_ids(&b, is_3d ? 3 : 2); nir_ssa_def *offset = - nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = 16); + nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = is_3d ? 12 : 8); nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16); nir_ssa_def *pos_x = nir_channel(&b, global_id, 0); @@ -411,8 +411,8 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev) nir_ssa_def *global_id = get_global_ids(&b, 2); - nir_ssa_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 16); - nir_ssa_def *pitch = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range = 16); + nir_ssa_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); + nir_ssa_def *pitch = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range = 12); nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16); nir_ssa_def *pos_x = nir_channel(&b, global_id, 0); @@ -564,9 +564,9 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples) nir_ssa_def *global_id = get_global_ids(&b, is_3d ? 3 : 2); nir_ssa_def *src_offset = - nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = 24); + nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range = is_3d ? 12 : 8); nir_ssa_def *dst_offset = - nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 12), .range = 24); + nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 12), .range = is_3d ? 24 : 20); nir_ssa_def *src_coord = nir_iadd(&b, global_id, src_offset); nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa; @@ -762,7 +762,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev) nir_ssa_def *global_id = get_global_ids(&b, 2); - nir_ssa_def *src_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 24); + nir_ssa_def *src_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12); nir_ssa_def *dst_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 12), .range = 24); nir_ssa_def *src_stride = nir_channel(&b, src_offset, 2); @@ -917,7 +917,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples nir_ssa_def *global_id = get_global_ids(&b, 2); - nir_ssa_def *clear_val = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 20); + nir_ssa_def *clear_val = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 16); nir_ssa_def *layer = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 16), .range = 20); nir_ssa_def *comps[4]; @@ -1073,7 +1073,7 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev) nir_ssa_def *global_id = get_global_ids(&b, 2); - nir_ssa_def *clear_val = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 16); + nir_ssa_def *clear_val = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12); nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16); nir_ssa_def *global_x = nir_channel(&b, global_id, 0); diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index e7eba2bed0a..aa14b910e95 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -79,7 +79,7 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s nir_ssa_def *global_id = get_global_ids(&b, 2); - nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 16); + nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); nir_ssa_def *dst_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 16); nir_ssa_def *src_coord = nir_iadd(&b, global_id, src_offset); diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c index 4e2ac92e367..074cbecdc7a 100644 --- a/src/amd/vulkan/radv_meta_resolve_fs.c +++ b/src/amd/vulkan/radv_meta_resolve_fs.c @@ -48,7 +48,7 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp color_out->data.location = FRAG_RESULT_DATA0; nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3); - nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), 0, 8); + nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8); nir_ssa_def *pos_int = nir_f2i32(&b, pos_in); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index f4e11e903f8..d22fa903f4a 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -128,7 +128,7 @@ build_occlusion_query_shader(struct radv_device *device) unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; unsigned db_count = device->physical_device->rad_info.max_render_backends; - nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16); + nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 4); nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0); nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1); @@ -137,7 +137,7 @@ build_occlusion_query_shader(struct radv_device *device) nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16); nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id); - nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16); + nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 8); nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id); nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1); @@ -257,8 +257,8 @@ build_pipeline_statistics_query_shader(struct radv_device *device) nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset"); - nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16); - nir_ssa_def *stats_mask = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range = 16); + nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 4); + nir_ssa_def *stats_mask = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range = 12); nir_ssa_def *avail_offset = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16); nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0); @@ -268,7 +268,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device) nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2); nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id); - nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16); + nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 8); nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id); avail_offset = nir_iadd(&b, avail_offset, nir_imul_imm(&b, global_id, 4)); @@ -395,7 +395,7 @@ build_tfb_query_shader(struct radv_device *device) nir_store_var(&b, result, nir_vec2(&b, nir_imm_int64(&b, 0), nir_imm_int64(&b, 0)), 0x3); nir_store_var(&b, available, nir_imm_false(&b), 0x1); - nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16); + nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 4); /* Load resources. */ nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0); @@ -407,7 +407,7 @@ build_tfb_query_shader(struct radv_device *device) /* Compute src/dst strides. */ nir_ssa_def *input_stride = nir_imm_int(&b, 32); nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id); - nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16); + nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 8); nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id); /* Load data from the query pool. */ @@ -515,7 +515,7 @@ build_timestamp_query_shader(struct radv_device *device) nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1); nir_store_var(&b, available, nir_imm_false(&b), 0x1); - nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 16); + nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range = 4); /* Load resources. */ nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0); @@ -527,7 +527,7 @@ build_timestamp_query_shader(struct radv_device *device) /* Compute src/dst strides. */ nir_ssa_def *input_stride = nir_imm_int(&b, 8); nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id); - nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 16); + nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range = 8); nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id); /* Load data from the query pool. */