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r600/sfn: use cacheless op for coherent image write

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7142>
This commit is contained in:
Gert Wollny
2020-10-07 14:06:43 +02:00
committed by Marge Bot
parent 02e39b737a
commit 92a4d45bee
4 changed files with 18 additions and 9 deletions
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15
src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp
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@@ -357,7 +357,9 @@ bool EmitSSBOInstruction::emit_store_ssbo(const nir_intrinsic_instr* instr)
auto values = vec_from_nir_with_fetch_constant(instr->src[0],
(1 << nir_src_num_components(instr->src[0])) - 1, {0,1,2,3}, true);
auto store = new RatInstruction(cf_mem_rat, RatInstruction::STORE_TYPED,
auto cf_op = cf_mem_rat;
//auto cf_op = nir_intrinsic_access(instr) & ACCESS_COHERENT ? cf_mem_rat_cacheless : cf_mem_rat;
auto store = new RatInstruction(cf_op, RatInstruction::STORE_TYPED,
values, addr_vec, m_ssbo_image_offset, rat_id, 1,
1, 0, false);
emit_instruction(store);
@@ -367,10 +369,11 @@ bool EmitSSBOInstruction::emit_store_ssbo(const nir_intrinsic_instr* instr)
emit_instruction(new AluInstruction(op1_mov, temp2.reg_i(0), from_nir(instr->src[0], i), write));
emit_instruction(new AluInstruction(op2_add_int, addr_vec.reg_i(0),
{addr_vec.reg_i(0), Value::one_i}, last_write));
store = new RatInstruction(cf_mem_rat, RatInstruction::STORE_TYPED,
store = new RatInstruction(cf_op, RatInstruction::STORE_TYPED,
temp2, addr_vec, 0, rat_id, 1,
1, 0, false);
emit_instruction(store);
if (!(nir_intrinsic_access(instr) & ACCESS_COHERENT))
m_store_ops.push_back(store);
}
#endif
@@ -399,10 +402,13 @@ EmitSSBOInstruction::emit_image_store(const nir_intrinsic_instr *intrin)
emit_instruction(new AluInstruction(op1_mov, coord.reg_i(1), coord.reg_i(2), {alu_last_instr, alu_write}));
}
auto store = new RatInstruction(cf_mem_rat, RatInstruction::STORE_TYPED, value, coord, imageid,
auto op = cf_mem_rat; //nir_intrinsic_access(intrin) & ACCESS_COHERENT ? cf_mem_rat_cacheless : cf_mem_rat;
auto store = new RatInstruction(op, RatInstruction::STORE_TYPED, value, coord, imageid,
image_offset, 1, 0xf, 0, false);
//if (!(nir_intrinsic_access(intrin) & ACCESS_COHERENT))
m_store_ops.push_back(store);
emit_instruction(store);
return true;
}
@@ -507,8 +513,9 @@ EmitSSBOInstruction::emit_image_load(const nir_intrinsic_instr *intrin)
from_nir(intrin->src[3], 0), {alu_last_instr, alu_write}));
}
}
auto cf_op = cf_mem_rat;// nir_intrinsic_access(intrin) & ACCESS_COHERENT ? cf_mem_rat_cacheless : cf_mem_rat;
auto store = new RatInstruction(cf_mem_rat, rat_op, m_rat_return_address, coord, imageid,
auto store = new RatInstruction(cf_op, rat_op, m_rat_return_address, coord, imageid,
image_offset, 1, 0xf, 0, true);
emit_instruction(store);
return fetch_return_value(intrin);

2
src/gallium/drivers/r600/sfn/sfn_instruction_gds.h
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@@ -168,6 +168,8 @@ public:
int data_swz(int chan) const {return m_data.chan_i(chan);}
ECFOpCode cf_opcode() const { return m_cf_opcode;}
void set_ack() {m_need_ack = true; }
private:

2
src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
View File

@@ -1050,7 +1050,7 @@ bool AssemblyFromShaderLegacyImpl::emit_rat(const RatInstruction& instr)
}
memset(&gds, 0, sizeof(struct r600_bytecode_gds));
r600_bytecode_add_cfinst(m_bc, CF_OP_MEM_RAT);
r600_bytecode_add_cfinst(m_bc, instr.cf_opcode());
auto cf = m_bc->cf_last;
cf->rat.id = rat_idx + m_shader->rat_base;
cf->rat.inst = instr.rat_op();

4
src/gallium/drivers/r600/sfn/sfn_nir.cpp
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@@ -918,8 +918,8 @@ int r600_shader_from_nir(struct r600_context *rctx,
} else {
r600::sfn_log << r600::SfnLog::shader_info << "This is not a Geometry shader\n";
}
if (pipeshader->shader.bc.ngpr < 4)
pipeshader->shader.bc.ngpr = 4;
if (pipeshader->shader.bc.ngpr < 6)
pipeshader->shader.bc.ngpr = 6;
return 0;
}