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intel/compiler: Track latency/perf of LSC fences

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11759>
This commit is contained in:
Lionel Landwerlin
2021-05-25 11:31:10 +03:00
committed by Marge Bot
parent 48af341b36
commit 91dcbf1f56
2 changed files with 2 additions and 0 deletions
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1
src/intel/compiler/brw_ir_performance.cpp
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@@ -1106,6 +1106,7 @@ namespace {
10 /* XXX */, 100 /* XXX */, 0, 0, 10 /* XXX */, 100 /* XXX */, 0, 0,
0, 0); 0, 0);
case LSC_OP_FENCE:
case LSC_OP_ATOMIC_INC: case LSC_OP_ATOMIC_INC:
case LSC_OP_ATOMIC_DEC: case LSC_OP_ATOMIC_DEC:
case LSC_OP_ATOMIC_LOAD: case LSC_OP_ATOMIC_LOAD:

1
src/intel/compiler/brw_schedule_instructions.cpp
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@@ -538,6 +538,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
case LSC_OP_STORE_CMASK: case LSC_OP_STORE_CMASK:
latency = 300; latency = 300;
break; break;
case LSC_OP_FENCE:
case LSC_OP_ATOMIC_INC: case LSC_OP_ATOMIC_INC:
case LSC_OP_ATOMIC_DEC: case LSC_OP_ATOMIC_DEC:
case LSC_OP_ATOMIC_LOAD: case LSC_OP_ATOMIC_LOAD: