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radv: Update GFX9 user data regs for GS/tess.

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Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen
2017-10-16 18:09:25 +02:00
parent ce03c119ce
commit 91b033f4f6
4 changed files with 25 additions and 14 deletions
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14
src/amd/vulkan/radv_cmd_buffer.c
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@@ -503,7 +503,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
int idx, uint64_t va) int idx, uint64_t va)
{ {
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx); struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
if (loc->sgpr_idx == -1) if (loc->sgpr_idx == -1)
return; return;
assert(loc->num_sgprs == 2); assert(loc->num_sgprs == 2);
@@ -545,7 +545,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) { if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset; uint32_t offset;
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET); struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
if (loc->sgpr_idx == -1) if (loc->sgpr_idx == -1)
return; return;
assert(loc->num_sgprs == 1); assert(loc->num_sgprs == 1);
@@ -764,7 +764,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT); loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) { if (loc->sgpr_idx != -1) {
uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 4); assert(loc->num_sgprs == 4);
assert(!loc->indirect); assert(!loc->indirect);
radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4); radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
@@ -777,7 +777,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT); loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) { if (loc->sgpr_idx != -1) {
uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 1); assert(loc->num_sgprs == 1);
assert(!loc->indirect); assert(!loc->indirect);
@@ -787,7 +787,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT); loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
if (loc->sgpr_idx != -1) { if (loc->sgpr_idx != -1) {
uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
assert(loc->num_sgprs == 1); assert(loc->num_sgprs == 1);
assert(!loc->indirect); assert(!loc->indirect);
@@ -1487,7 +1487,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
gl_shader_stage stage) gl_shader_stage stage)
{ {
struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx]; struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect) if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
return; return;
@@ -2858,7 +2858,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned in
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX); struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
if (loc->sgpr_idx == -1) if (loc->sgpr_idx == -1)
continue; continue;
uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
} }

2
src/amd/vulkan/radv_pipeline.c
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@@ -2022,7 +2022,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE); AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) { if (loc->sgpr_idx != -1) {
pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id) if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
pipeline->graphics.vtx_emit_num = 3; pipeline->graphics.vtx_emit_num = 3;

19
src/amd/vulkan/radv_shader.c
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@@ -500,24 +500,35 @@ radv_shader_variant_destroy(struct radv_device *device,
} }
uint32_t uint32_t
radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class,
bool has_tess) bool has_gs, bool has_tess)
{ {
switch (stage) { switch (stage) {
case MESA_SHADER_FRAGMENT: case MESA_SHADER_FRAGMENT:
return R_00B030_SPI_SHADER_USER_DATA_PS_0; return R_00B030_SPI_SHADER_USER_DATA_PS_0;
case MESA_SHADER_VERTEX: case MESA_SHADER_VERTEX:
if (chip_class >= GFX9) {
return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
R_00B130_SPI_SHADER_USER_DATA_VS_0;
}
if (has_tess) if (has_tess)
return R_00B530_SPI_SHADER_USER_DATA_LS_0; return R_00B530_SPI_SHADER_USER_DATA_LS_0;
else else
return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
case MESA_SHADER_GEOMETRY: case MESA_SHADER_GEOMETRY:
return R_00B230_SPI_SHADER_USER_DATA_GS_0; return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
R_00B230_SPI_SHADER_USER_DATA_GS_0;
case MESA_SHADER_COMPUTE: case MESA_SHADER_COMPUTE:
return R_00B900_COMPUTE_USER_DATA_0; return R_00B900_COMPUTE_USER_DATA_0;
case MESA_SHADER_TESS_CTRL: case MESA_SHADER_TESS_CTRL:
return R_00B430_SPI_SHADER_USER_DATA_HS_0; return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
R_00B430_SPI_SHADER_USER_DATA_HS_0;
case MESA_SHADER_TESS_EVAL: case MESA_SHADER_TESS_EVAL:
if (chip_class >= GFX9) {
return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
R_00B130_SPI_SHADER_USER_DATA_VS_0;
}
if (has_gs) if (has_gs)
return R_00B330_SPI_SHADER_USER_DATA_ES_0; return R_00B330_SPI_SHADER_USER_DATA_ES_0;
else else

4
src/amd/vulkan/radv_shader.h
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@@ -104,8 +104,8 @@ radv_shader_variant_destroy(struct radv_device *device,
struct radv_shader_variant *variant); struct radv_shader_variant *variant);
uint32_t uint32_t
radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class,
bool has_tess); bool has_gs, bool has_tess);
const char * const char *
radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage); radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);