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radeonsi/gfx11: don't set COMPR for exports, use 0x3 channel mask instead

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Marek Olšák
2021-12-17 12:30:58 -05:00
committed by Marge Bot
parent 6e537680c4
commit 91a7f43f0b
2 changed files with 15 additions and 9 deletions
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16
src/amd/llvm/ac_llvm_build.c
View File

@@ -1970,6 +1970,8 @@ void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
args[1] = LLVMConstInt(ctx->i32, a->enabled_channels, 0);
if (a->compr) {
assert(ctx->chip_class < GFX11);
args[2] = LLVMBuildBitCast(ctx->builder, a->out[0], ctx->v2i16, "");
args[3] = LLVMBuildBitCast(ctx->builder, a->out[1], ctx->v2i16, "");
args[4] = LLVMConstInt(ctx->i1, a->done, 0);
@@ -1977,10 +1979,10 @@ void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
ac_build_intrinsic(ctx, "llvm.amdgcn.exp.compr.v2i16", ctx->voidt, args, 6, 0);
} else {
args[2] = a->out[0];
args[3] = a->out[1];
args[4] = a->out[2];
args[5] = a->out[3];
args[2] = LLVMBuildBitCast(ctx->builder, a->out[0], ctx->f32, "");
args[3] = LLVMBuildBitCast(ctx->builder, a->out[1], ctx->f32, "");
args[4] = LLVMBuildBitCast(ctx->builder, a->out[2], ctx->f32, "");
args[5] = LLVMBuildBitCast(ctx->builder, a->out[3], ctx->f32, "");
args[6] = LLVMConstInt(ctx->i1, a->done, 0);
args[7] = LLVMConstInt(ctx->i1, a->valid_mask, 0);
@@ -4255,19 +4257,19 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR
if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
assert(!depth);
args->compr = 1; /* COMPR flag */
args->compr = ctx->chip_class < GFX11; /* COMPR flag */
if (stencil) {
/* Stencil should be in X[23:16]. */
stencil = ac_to_integer(ctx, stencil);
stencil = LLVMBuildShl(ctx->builder, stencil, LLVMConstInt(ctx->i32, 16, 0), "");
args->out[0] = ac_to_float(ctx, stencil);
mask |= 0x3;
mask |= ctx->chip_class >= GFX11 ? 0x1 : 0x3;
}
if (samplemask) {
/* SampleMask should be in Y[15:0]. */
args->out[1] = samplemask;
mask |= 0xc;
mask |= ctx->chip_class >= GFX11 ? 0x2 : 0xc;
}
} else {
if (depth) {

8
src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
View File

@@ -384,7 +384,6 @@ static bool si_llvm_init_ps_export_args(struct si_shader_context *ctx, LLVMValue
packed = packf(&ctx->ac, pack_args);
args->out[chan] = ac_to_float(&ctx->ac, packed);
}
args->compr = 1; /* COMPR flag */
}
/* Pack i16/u16. */
if (packi) {
@@ -396,7 +395,12 @@ static bool si_llvm_init_ps_export_args(struct si_shader_context *ctx, LLVMValue
packed = packi(&ctx->ac, pack_args, is_int8 ? 8 : is_int10 ? 10 : 16, chan == 1);
args->out[chan] = ac_to_float(&ctx->ac, packed);
}
args->compr = 1; /* COMPR flag */
}
if (packf || packi) {
if (ctx->screen->info.chip_class >= GFX11)
args->enabled_channels = 0x3;
else
args->compr = 1; /* COMPR flag */
}
return true;