broadcom/compiler: rename is_ldunif_dst to try_rf0
We flag nodes used to ldunif dst so we can try and favor allocating rf0 to them, so be more explicit about its purpose. Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31355>
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@@ -619,7 +619,7 @@ struct v3d_ra_node_info {
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bool payload_conflict;
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/* V3D 7.x */
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bool is_ldunif_dst;
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bool try_rf0;
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} *info;
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uint32_t alloc_count;
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};
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@@ -409,7 +409,7 @@ add_node(struct v3d_compile *c, uint32_t temp, uint8_t class_bits)
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/* We fill the node priority after we are done inserting spills */
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c->nodes.info[node].class_bits = class_bits;
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c->nodes.info[node].priority = 0;
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c->nodes.info[node].is_ldunif_dst = false;
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c->nodes.info[node].try_rf0 = false;
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c->nodes.info[node].is_program_end = false;
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c->nodes.info[node].unused = false;
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c->nodes.info[node].payload_conflict = false;
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@@ -965,7 +965,7 @@ v3d_ra_select_rf(struct v3d_ra_select_callback_data *v3d_ra,
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* cond field to encode the dst and would prevent merge with
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* instructions that use cond flags).
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*/
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if (v3d_ra->nodes->info[node].is_ldunif_dst &&
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if (v3d_ra->nodes->info[node].try_rf0 &&
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BITSET_TEST(regs, v3d_ra->phys_index)) {
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assert(v3d_ra->devinfo->ver >= 71);
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*out = v3d_ra->phys_index;
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@@ -1320,7 +1320,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c,
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if (inst->qpu.sig.ldunif || inst->qpu.sig.ldunifa) {
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const uint32_t dst_n =
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temp_to_node(c, inst->dst.index);
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c->nodes.info[dst_n].is_ldunif_dst = true;
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c->nodes.info[dst_n].try_rf0 = true;
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}
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}
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}
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@@ -1433,7 +1433,7 @@ v3d_register_allocate(struct v3d_compile *c)
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* without accumulators that can have implicit writes to phys regs.
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*/
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for (uint32_t i = 0; i < num_ra_nodes; i++) {
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c->nodes.info[i].is_ldunif_dst = false;
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c->nodes.info[i].try_rf0 = false;
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c->nodes.info[i].is_program_end = false;
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c->nodes.info[i].unused = false;
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c->nodes.info[i].priority = 0;
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