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intel/compiler: Add brw_get_compiler_config_value for disk cache

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During code review, Jason pointed out that:

2b3064c073 "i965, anv: Use INTEL_DEBUG for disk_cache driver flags"

Didn't account for INTEL_SCALER_* environment variables.

To fix this, let the compiler return the disk_cache driver flags.

Another possible fix would be to pull the INTEL_SCALER_* into
INTEL_DEBUG bits, but as we are currently using 41 of 64 bits, I
didn't think it was a good use of 4 more of these bits. (5 since
INTEL_PRECISE_TRIG needs to be accounted for as well.)

Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen
2018-07-25 14:31:05 -07:00
parent 3887700dfd
commit 8fcdb71d8c
4 changed files with 43 additions and 2 deletions
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27
src/intel/compiler/brw_compiler.c
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@@ -181,6 +181,33 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
return compiler;
}
static void
insert_u64_bit(uint64_t *val, bool add)
{
*val = (*val << 1) | !!add;
}
uint64_t
brw_get_compiler_config_value(const struct brw_compiler *compiler)
{
uint64_t config = 0;
insert_u64_bit(&config, compiler->precise_trig);
if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
}
uint64_t debug_bits = INTEL_DEBUG;
uint64_t mask = DEBUG_DISK_CACHE_MASK;
while (mask != 0) {
const uint64_t bit = 1ULL << (ffsll(mask) - 1);
insert_u64_bit(&config, (debug_bits & bit) != 0);
mask &= ~bit;
}
return config;
}
unsigned
brw_prog_data_size(gl_shader_stage stage)
{