OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/fs: Lower untyped float atomic messages to LSC when available

Browse Source 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
This commit is contained in:
Sagar Ghuge
2021-04-29 20:50:42 -07:00
committed by Marge Bot
parent bd40a1e8c9
commit 8f82c8aa1a
3 changed files with 33 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
src/intel/compiler/brw_fs.cpp
View File

@@ -5878,6 +5878,21 @@ brw_atomic_op_to_lsc_atomic_op(unsigned op)
}
}
static enum lsc_opcode
brw_atomic_op_to_lsc_fatomic_op(uint32_t aop)
{
switch(aop) {
case BRW_AOP_FMAX:
return LSC_OP_ATOMIC_FMAX;
case BRW_AOP_FMIN:
return LSC_OP_ATOMIC_FMIN;
case BRW_AOP_FCMPWR:
return LSC_OP_ATOMIC_FCMPXCHG;
default:
unreachable("Unsupported float atomic opcode");
}
}
static void
lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
{
@@ -5952,14 +5967,17 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
false /* has_dest */);
break;
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: {
/* Bspec: Atomic instruction -> Cache section:
*
* Atomic messages are always forced to "un-cacheable" in the L1
* cache.
*/
inst->desc = lsc_msg_desc(devinfo,
brw_atomic_op_to_lsc_atomic_op(arg.ud),
inst->exec_size,
enum lsc_opcode opcode =
inst->opcode == SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL ?
brw_atomic_op_to_lsc_fatomic_op(arg.ud) :
brw_atomic_op_to_lsc_atomic_op(arg.ud);
inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size,
surf_type, LSC_ADDR_SIZE_A32,
1 /* num_coordinates */,
LSC_DATA_SIZE_D32, 1 /* num_channels */,
@@ -5967,6 +5985,7 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
LSC_CACHE_STORE_L1UC_L3WB,
!inst->dst.is_null());
break;
}
default:
unreachable("Unknown surface logical instruction");
}
@@ -6583,6 +6602,7 @@ fs_visitor::lower_logical_sends()
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
if (devinfo->has_lsc) {
lower_lsc_surface_logical_send(ibld, inst);
break;
@@ -6591,7 +6611,6 @@ fs_visitor::lower_logical_sends()
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:

5
src/intel/compiler/brw_ir_performance.cpp
View File

@@ -1115,6 +1115,11 @@ namespace {
case LSC_OP_ATOMIC_UMIN:
case LSC_OP_ATOMIC_UMAX:
case LSC_OP_ATOMIC_CMPXCHG:
case LSC_OP_ATOMIC_FADD:
case LSC_OP_ATOMIC_FSUB:
case LSC_OP_ATOMIC_FMIN:
case LSC_OP_ATOMIC_FMAX:
case LSC_OP_ATOMIC_FCMPXCHG:
case LSC_OP_ATOMIC_AND:
case LSC_OP_ATOMIC_OR:
case LSC_OP_ATOMIC_XOR:

5
src/intel/compiler/brw_schedule_instructions.cpp
View File

@@ -547,6 +547,11 @@ schedule_node::set_latency_gfx7(bool is_haswell)
case LSC_OP_ATOMIC_UMIN:
case LSC_OP_ATOMIC_UMAX:
case LSC_OP_ATOMIC_CMPXCHG:
case LSC_OP_ATOMIC_FADD:
case LSC_OP_ATOMIC_FSUB:
case LSC_OP_ATOMIC_FMIN:
case LSC_OP_ATOMIC_FMAX:
case LSC_OP_ATOMIC_FCMPXCHG:
case LSC_OP_ATOMIC_AND:
case LSC_OP_ATOMIC_OR:
case LSC_OP_ATOMIC_XOR: