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intel: Use the NIR lowering for isign.

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Drops one instruction from fs-sign-int.shader_test.  No change in
shader-db due to it having 0 instances of sign(genIType).  This may hurt
isign64 if algebraic runs before int64 lowering, but I wasn't sure how to
mark the algebraic opt as "every bit size but 64".

v2: Update commit message about shader-db.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
This commit is contained in:
Eric Anholt
2019-02-06 13:26:17 -08:00
parent 3f22b35a43
commit 8f3694e1ab
3 changed files with 1 additions and 31 deletions
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1
src/intel/compiler/brw_compiler.c
View File

@@ -41,6 +41,7 @@
.lower_usub_borrow = true, \
.lower_fdiv = true, \
.lower_flrp64 = true, \
.lower_isign = true, \
.lower_ldexp = true, \
.lower_cs_local_id_from_index = true, \
.lower_device_index_to_zero = true, \

19
src/intel/compiler/brw_fs_nir.cpp
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@@ -875,25 +875,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
}
case nir_op_isign: {
/* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
* -> non-negative val generates 0x00000000.
* Predicated OR sets 1 if val is positive.
*/
uint32_t bit_size = nir_dest_bit_size(instr->dest.dest);
assert(bit_size == 32 || bit_size == 16);
fs_reg zero = bit_size == 32 ? brw_imm_d(0) : brw_imm_w(0);
fs_reg one = bit_size == 32 ? brw_imm_d(1) : brw_imm_w(1);
fs_reg shift = bit_size == 32 ? brw_imm_d(31) : brw_imm_w(15);
bld.CMP(bld.null_reg_d(), op[0], zero, BRW_CONDITIONAL_G);
bld.ASR(result, op[0], shift);
inst = bld.OR(result, result, one);
inst->predicate = BRW_PREDICATE_NORMAL;
break;
}
case nir_op_frcp:
inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]);
inst->saturate = instr->dest.saturate;

12
src/intel/compiler/brw_vec4_nir.cpp
View File

@@ -1735,18 +1735,6 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
}
break;
case nir_op_isign:
/* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
* -> non-negative val generates 0x00000000.
* Predicated OR sets 1 if val is positive.
*/
assert(nir_dest_bit_size(instr->dest.dest) < 64);
emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G));
emit(ASR(dst, op[0], brw_imm_d(31)));
inst = emit(OR(dst, src_reg(dst), brw_imm_d(1)));
inst->predicate = BRW_PREDICATE_NORMAL;
break;
case nir_op_ishl:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
emit(SHL(dst, op[0], op[1]));