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radeonsi: move emitting VGT_TF_PARAM into gfx10_emit_shader_ngg

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so that it's next to other registers instead of separated

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
This commit is contained in:
Marek Olšák
2023-10-25 04:23:19 -04:00
committed by Marge Bot
parent 870568b512
commit 8edb0c7038
1 changed files with 7 additions and 15 deletions
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22
src/gallium/drivers/radeonsi/si_state_shaders.cpp
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@@ -1169,7 +1169,7 @@ bool gfx10_is_ngg_passthrough(struct si_shader *shader)
return sel->stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling; return sel->stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling;
} }
/* Common tail code for NGG primitive shaders. */ template <enum si_has_tess HAS_TESS>
static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index) static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
{ {
struct si_shader *shader = sctx->queued.named.gs; struct si_shader *shader = sctx->queued.named.gs;
@@ -1178,6 +1178,10 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
shader->ngg.esgs_vertex_stride); shader->ngg.esgs_vertex_stride);
radeon_begin(&sctx->gfx_cs); radeon_begin(&sctx->gfx_cs);
if (HAS_TESS) {
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
}
radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
shader->ngg.ge_max_output_per_subgroup); shader->ngg.ge_max_output_per_subgroup);
@@ -1235,18 +1239,6 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
radeon_end(); radeon_end();
} }
static void gfx10_emit_shader_ngg_tess(struct si_context *sctx, unsigned index)
{
struct si_shader *shader = sctx->queued.named.gs;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
radeon_end_update_context_roll(sctx);
gfx10_emit_shader_ngg(sctx, index);
}
unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key) unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key)
{ {
if (gs->stage == MESA_SHADER_GEOMETRY) if (gs->stage == MESA_SHADER_GEOMETRY)
@@ -1319,9 +1311,9 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
return; return;
if (es_stage == MESA_SHADER_TESS_EVAL) if (es_stage == MESA_SHADER_TESS_EVAL)
pm4->atom.emit = gfx10_emit_shader_ngg_tess; pm4->atom.emit = gfx10_emit_shader_ngg<TESS_ON>;
else else
pm4->atom.emit = gfx10_emit_shader_ngg; pm4->atom.emit = gfx10_emit_shader_ngg<TESS_OFF>;
va = shader->bo->gpu_address; va = shader->bo->gpu_address;