From 8edb0c70387b9e1ed1a1e8a97948c6219cf9f696 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Wed, 25 Oct 2023 04:23:19 -0400
Subject: [PATCH] radeonsi: move emitting VGT_TF_PARAM into
 gfx10_emit_shader_ngg

so that it's next to other registers instead of separated

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
---
 .../drivers/radeonsi/si_state_shaders.cpp     | 22 ++++++-------------
 1 file changed, 7 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index d7a939d0201..b2116d31695 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -1169,7 +1169,7 @@ bool gfx10_is_ngg_passthrough(struct si_shader *shader)
    return sel->stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling;
 }
 
-/* Common tail code for NGG primitive shaders. */
+template <enum si_has_tess HAS_TESS>
 static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
 {
    struct si_shader *shader = sctx->queued.named.gs;
@@ -1178,6 +1178,10 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
              shader->ngg.esgs_vertex_stride);
 
    radeon_begin(&sctx->gfx_cs);
+   if (HAS_TESS) {
+      radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
+                                 shader->vgt_tf_param);
+   }
    radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
                               SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
                               shader->ngg.ge_max_output_per_subgroup);
@@ -1235,18 +1239,6 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
    radeon_end();
 }
 
-static void gfx10_emit_shader_ngg_tess(struct si_context *sctx, unsigned index)
-{
-   struct si_shader *shader = sctx->queued.named.gs;
-
-   radeon_begin(&sctx->gfx_cs);
-   radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
-                              shader->vgt_tf_param);
-   radeon_end_update_context_roll(sctx);
-
-   gfx10_emit_shader_ngg(sctx, index);
-}
-
 unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key)
 {
    if (gs->stage == MESA_SHADER_GEOMETRY)
@@ -1319,9 +1311,9 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
       return;
 
    if (es_stage == MESA_SHADER_TESS_EVAL)
-      pm4->atom.emit = gfx10_emit_shader_ngg_tess;
+      pm4->atom.emit = gfx10_emit_shader_ngg<TESS_ON>;
    else
-      pm4->atom.emit = gfx10_emit_shader_ngg;
+      pm4->atom.emit = gfx10_emit_shader_ngg<TESS_OFF>;
 
    va = shader->bo->gpu_address;