intel/compiler: validate region restrictions for mixed float mode
v2: - Adapted unit tests to make them consistent with the changes done to the validation of half-float conversions. v3 (Curro): - Check all the accummulators - Constify declarations - Do not check src1 type in single-source instructions. - Check for all instructions that read accumulator (either implicitly or explicitly) - Check restrictions in src1 too. - Merge conditional block - Add invalid test case. v4 (Curro): - Assert on 3-src instructions, as they are not validated. - Get rid of types_are_mixed_float(), as we know instruction is mixed float at that point. - Remove conditions from not verified case. - Fix brackets on conditional. Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Iago Toral Quiroga
committed by
Juan A. Suarez Romero
Juan A. Suarez Romero
parent
58d6417e59
commit
8ed6d74c92
@@ -170,6 +170,20 @@ src1_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
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brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
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}
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static bool
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src0_is_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
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(brw_inst_src0_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR;
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}
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static bool
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src1_is_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
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(brw_inst_src1_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR;
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}
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static bool
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src0_is_grf(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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@@ -275,6 +289,24 @@ sources_not_null(const struct gen_device_info *devinfo,
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return error_msg;
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}
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static bool
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inst_uses_src_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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/* Check instructions that use implicit accumulator sources */
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switch (brw_inst_opcode(devinfo, inst)) {
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case BRW_OPCODE_MAC:
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case BRW_OPCODE_MACH:
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case BRW_OPCODE_SADA2:
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return true;
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}
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/* FIXME: support 3-src instructions */
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unsigned num_sources = num_sources_from_inst(devinfo, inst);
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assert(num_sources < 3);
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return src0_is_acc(devinfo, inst) || (num_sources > 1 && src1_is_acc(devinfo, inst));
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}
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static struct string
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send_restrictions(const struct gen_device_info *devinfo,
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const brw_inst *inst)
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@@ -938,6 +970,223 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
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return error_msg;
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}
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static struct string
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special_restrictions_for_mixed_float_mode(const struct gen_device_info *devinfo,
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const brw_inst *inst)
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{
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struct string error_msg = { .str = NULL, .len = 0 };
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const unsigned opcode = brw_inst_opcode(devinfo, inst);
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const unsigned num_sources = num_sources_from_inst(devinfo, inst);
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if (num_sources >= 3)
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return error_msg;
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if (!is_mixed_float(devinfo, inst))
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return error_msg;
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
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bool is_align16 = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16;
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enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
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enum brw_reg_type src1_type = num_sources > 1 ?
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brw_inst_src1_type(devinfo, inst) : 0;
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enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
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unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
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bool dst_is_packed = is_packed(exec_size * dst_stride, exec_size, dst_stride);
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "Indirect addressing on source is not supported when source and
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* destination data types are mixed float."
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*/
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ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT ||
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(num_sources > 1 &&
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brw_inst_src1_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT),
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"Indirect addressing on source is not supported when source and "
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"destination data types are mixed float");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "No SIMD16 in mixed mode when destination is f32. Instruction
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* execution size must be no more than 8."
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*/
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ERROR_IF(exec_size > 8 && dst_type == BRW_REGISTER_TYPE_F,
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"Mixed float mode with 32-bit float destination is limited "
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"to SIMD8");
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if (is_align16) {
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "In Align16 mode, when half float and float data types are mixed
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* between source operands OR between source and destination operands,
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* the register content are assumed to be packed."
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*
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* Since Align16 doesn't have a concept of horizontal stride (or width),
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* it means that vertical stride must always be 4, since 0 and 2 would
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* lead to replicated data, and any other value is disallowed in Align16.
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*/
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ERROR_IF(brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
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"Align16 mixed float mode assumes packed data (vstride must be 4");
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ERROR_IF(num_sources >= 2 &&
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brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4,
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"Align16 mixed float mode assumes packed data (vstride must be 4");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "For Align16 mixed mode, both input and output packed f16 data
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* must be oword aligned, no oword crossing in packed f16."
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*
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* The previous rule requires that Align16 operands are always packed,
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* and since there is only one bit for Align16 subnr, which represents
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* offsets 0B and 16B, this rule is always enforced and we don't need to
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* validate it.
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*/
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "No SIMD16 in mixed mode when destination is packed f16 for both
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* Align1 and Align16."
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*
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* And:
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*
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* "In Align16 mode, when half float and float data types are mixed
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* between source operands OR between source and destination operands,
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* the register content are assumed to be packed."
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*
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* Which implies that SIMD16 is not available in Align16. This is further
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* confirmed by:
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*
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* "For Align16 mixed mode, both input and output packed f16 data
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* must be oword aligned, no oword crossing in packed f16"
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*
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* Since oword-aligned packed f16 data would cross oword boundaries when
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* the execution size is larger than 8.
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*/
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ERROR_IF(exec_size > 8, "Align16 mixed float mode is limited to SIMD8");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "No accumulator read access for Align16 mixed float."
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*/
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ERROR_IF(inst_uses_src_acc(devinfo, inst),
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"No accumulator read access for Align16 mixed float");
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} else {
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assert(!is_align16);
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "No SIMD16 in mixed mode when destination is packed f16 for both
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* Align1 and Align16."
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*/
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ERROR_IF(exec_size > 8 && dst_is_packed &&
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dst_type == BRW_REGISTER_TYPE_HF,
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"Align1 mixed float mode is limited to SIMD8 when destination "
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"is packed half-float");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "Math operations for mixed mode:
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* - In Align1, f16 inputs need to be strided"
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*/
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if (opcode == BRW_OPCODE_MATH) {
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if (src0_type == BRW_REGISTER_TYPE_HF) {
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ERROR_IF(STRIDE(brw_inst_src0_hstride(devinfo, inst)) <= 1,
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"Align1 mixed mode math needs strided half-float inputs");
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}
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if (num_sources >= 2 && src1_type == BRW_REGISTER_TYPE_HF) {
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ERROR_IF(STRIDE(brw_inst_src1_hstride(devinfo, inst)) <= 1,
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"Align1 mixed mode math needs strided half-float inputs");
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}
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}
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if (dst_type == BRW_REGISTER_TYPE_HF && dst_stride == 1) {
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "In Align1, destination stride can be smaller than execution
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* type. When destination is stride of 1, 16 bit packed data is
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* updated on the destination. However, output packed f16 data
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* must be oword aligned, no oword crossing in packed f16."
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*
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* The requirement of not crossing oword boundaries for 16-bit oword
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* aligned data means that execution size is limited to 8.
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*/
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unsigned subreg;
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if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT)
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subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
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else
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subreg = brw_inst_dst_ia_subreg_nr(devinfo, inst);
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ERROR_IF(subreg % 16 != 0,
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"Align1 mixed mode packed half-float output must be "
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"oword aligned");
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ERROR_IF(exec_size > 8,
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"Align1 mixed mode packed half-float output must not "
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"cross oword boundaries (max exec size is 8)");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "When source is float or half float from accumulator register and
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* destination is half float with a stride of 1, the source must
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* register aligned. i.e., source must have offset zero."
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*
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* Align16 mixed float mode doesn't allow accumulator access on sources,
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* so we only need to check this for Align1.
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*/
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if (src0_is_acc(devinfo, inst) &&
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(src0_type == BRW_REGISTER_TYPE_F ||
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src0_type == BRW_REGISTER_TYPE_HF)) {
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ERROR_IF(brw_inst_src0_da1_subreg_nr(devinfo, inst) != 0,
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"Mixed float mode requires register-aligned accumulator "
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"source reads when destination is packed half-float");
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}
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if (num_sources > 1 &&
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src1_is_acc(devinfo, inst) &&
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(src1_type == BRW_REGISTER_TYPE_F ||
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src1_type == BRW_REGISTER_TYPE_HF)) {
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ERROR_IF(brw_inst_src1_da1_subreg_nr(devinfo, inst) != 0,
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"Mixed float mode requires register-aligned accumulator "
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"source reads when destination is packed half-float");
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}
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}
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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*
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* "No swizzle is allowed when an accumulator is used as an implicit
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* source or an explicit source in an instruction. i.e. when
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* destination is half float with an implicit accumulator source,
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* destination stride needs to be 2."
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*
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* FIXME: it is not quite clear what the first sentence actually means
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* or its link to the implication described after it, so we only
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* validate the explicit implication, which is clearly described.
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*/
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if (dst_type == BRW_REGISTER_TYPE_HF &&
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inst_uses_src_acc(devinfo, inst)) {
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ERROR_IF(dst_stride != 2,
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"Mixed float mode with implicit/explicit accumulator "
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"source and half-float destination requires a stride "
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"of 2 on the destination");
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}
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}
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return error_msg;
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}
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/**
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* Creates an \p access_mask for an \p exec_size, \p element_size, and a region
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*
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@@ -1576,6 +1825,7 @@ brw_validate_instructions(const struct gen_device_info *devinfo,
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CHECK(send_restrictions);
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CHECK(general_restrictions_based_on_operand_types);
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CHECK(general_restrictions_on_region_parameters);
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CHECK(special_restrictions_for_mixed_float_mode);
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CHECK(region_alignment_rules);
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CHECK(vector_immediate_restrictions);
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CHECK(special_requirements_for_handling_double_precision_data_types);
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@@ -1019,6 +1019,636 @@ TEST_P(validation_test, half_float_conversion)
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}
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}
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TEST_P(validation_test, mixed_float_source_indirect_addressing)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool dst_indirect;
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bool src0_indirect;
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bool expected_result;
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} inst[] = {
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#define INST(dst_type, src0_type, src1_type, \
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dst_stride, dst_indirect, src0_indirect, expected_result) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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dst_indirect, \
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src0_indirect, \
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expected_result, \
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}
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/* Source and dest are mixed float: indirect src addressing not allowed */
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INST(HF, F, F, 2, false, false, true),
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INST(HF, F, F, 2, true, false, true),
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INST(HF, F, F, 2, false, true, false),
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INST(HF, F, F, 2, true, true, false),
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INST( F, HF, F, 1, false, false, true),
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INST( F, HF, F, 1, true, false, true),
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INST( F, HF, F, 1, false, true, false),
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INST( F, HF, F, 1, true, true, false),
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INST(HF, HF, F, 2, false, false, true),
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INST(HF, HF, F, 2, true, false, true),
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INST(HF, HF, F, 2, false, true, false),
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INST(HF, HF, F, 2, true, true, false),
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INST( F, F, HF, 1, false, false, true),
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INST( F, F, HF, 1, true, false, true),
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INST( F, F, HF, 1, false, true, false),
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INST( F, F, HF, 1, true, true, false),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_dst_address_mode(&devinfo, last_inst, inst[i].dst_indirect);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_src0_address_mode(&devinfo, last_inst, inst[i].src0_indirect);
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EXPECT_EQ(inst[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_simd16)
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{
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static const struct {
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unsigned exec_size;
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool expected_result;
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} inst[] = {
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#define INST(exec_size, dst_type, src0_type, src1_type, \
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dst_stride, expected_result) \
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{ \
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BRW_EXECUTE_##exec_size, \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src0_type, \
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BRW_REGISTER_TYPE_##src1_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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expected_result, \
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}
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/* No SIMD16 in mixed mode when destination is packed f16 */
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INST( 8, HF, F, HF, 2, true),
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INST(16, HF, HF, F, 2, true),
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INST(16, HF, HF, F, 1, false),
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INST(16, HF, F, HF, 1, false),
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/* No SIMD16 in mixed mode when destination is f32 */
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INST( 8, F, HF, F, 1, true),
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INST( 8, F, F, HF, 1, true),
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INST(16, F, HF, F, 1, false),
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INST(16, F, F, HF, 1, false),
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#undef INST
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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brw_ADD(p, retype(g0, inst[i].dst_type),
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retype(g0, inst[i].src0_type),
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retype(g0, inst[i].src1_type));
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brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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EXPECT_EQ(inst[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, mixed_float_align1_packed_fp16_dst_acc_read_offset_0)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src0_type;
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enum brw_reg_type src1_type;
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unsigned dst_stride;
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bool read_acc;
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unsigned subnr;
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bool expected_result_bdw;
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bool expected_result_chv_skl;
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} inst[] = {
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#define INST(dst_type, src0_type, src1_type, dst_stride, read_acc, subnr, \
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expected_result_bdw, expected_result_chv_skl) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_HORIZONTAL_STRIDE_##dst_stride, \
|
||||
read_acc, \
|
||||
subnr, \
|
||||
expected_result_bdw, \
|
||||
expected_result_chv_skl, \
|
||||
}
|
||||
|
||||
/* Destination is not packed */
|
||||
INST(HF, HF, F, 2, true, 0, true, true),
|
||||
INST(HF, HF, F, 2, true, 2, true, true),
|
||||
INST(HF, HF, F, 2, true, 4, true, true),
|
||||
INST(HF, HF, F, 2, true, 8, true, true),
|
||||
INST(HF, HF, F, 2, true, 16, true, true),
|
||||
|
||||
/* Destination is packed, we don't read acc */
|
||||
INST(HF, HF, F, 1, false, 0, false, true),
|
||||
INST(HF, HF, F, 1, false, 2, false, true),
|
||||
INST(HF, HF, F, 1, false, 4, false, true),
|
||||
INST(HF, HF, F, 1, false, 8, false, true),
|
||||
INST(HF, HF, F, 1, false, 16, false, true),
|
||||
|
||||
/* Destination is packed, we read acc */
|
||||
INST(HF, HF, F, 1, true, 0, false, false),
|
||||
INST(HF, HF, F, 1, true, 2, false, false),
|
||||
INST(HF, HF, F, 1, true, 4, false, false),
|
||||
INST(HF, HF, F, 1, true, 8, false, false),
|
||||
INST(HF, HF, F, 1, true, 16, false, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8)
|
||||
return;
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
|
||||
|
||||
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, inst[i].subnr);
|
||||
|
||||
if (devinfo.is_cherryview || devinfo.gen >= 9)
|
||||
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
|
||||
else
|
||||
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_fp16_dest_with_acc)
|
||||
{
|
||||
static const struct {
|
||||
unsigned exec_size;
|
||||
unsigned opcode;
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned dst_stride;
|
||||
bool read_acc;
|
||||
bool expected_result_bdw;
|
||||
bool expected_result_chv_skl;
|
||||
} inst[] = {
|
||||
#define INST(exec_size, opcode, dst_type, src0_type, src1_type, \
|
||||
dst_stride, read_acc,expected_result_bdw, \
|
||||
expected_result_chv_skl) \
|
||||
{ \
|
||||
BRW_EXECUTE_##exec_size, \
|
||||
BRW_OPCODE_##opcode, \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_HORIZONTAL_STRIDE_##dst_stride, \
|
||||
read_acc, \
|
||||
expected_result_bdw, \
|
||||
expected_result_chv_skl, \
|
||||
}
|
||||
|
||||
/* Packed fp16 dest with implicit acc needs hstride=2 */
|
||||
INST(8, MAC, HF, HF, F, 1, false, false, false),
|
||||
INST(8, MAC, HF, HF, F, 2, false, true, true),
|
||||
INST(8, MAC, HF, F, HF, 1, false, false, false),
|
||||
INST(8, MAC, HF, F, HF, 2, false, true, true),
|
||||
|
||||
/* Packed fp16 dest with explicit acc needs hstride=2 */
|
||||
INST(8, ADD, HF, HF, F, 1, true, false, false),
|
||||
INST(8, ADD, HF, HF, F, 2, true, true, true),
|
||||
INST(8, ADD, HF, F, HF, 1, true, false, false),
|
||||
INST(8, ADD, HF, F, HF, 2, true, true, true),
|
||||
|
||||
/* If destination is not fp16, restriction doesn't apply */
|
||||
INST(8, MAC, F, HF, F, 1, false, true, true),
|
||||
INST(8, MAC, F, HF, F, 2, false, true, true),
|
||||
|
||||
/* If there is no implicit/explicit acc, restriction doesn't apply */
|
||||
INST(8, ADD, HF, HF, F, 1, false, false, true),
|
||||
INST(8, ADD, HF, HF, F, 2, false, true, true),
|
||||
INST(8, ADD, HF, F, HF, 1, false, false, true),
|
||||
INST(8, ADD, HF, F, HF, 2, false, true, true),
|
||||
INST(8, ADD, F, HF, F, 1, false, true, true),
|
||||
INST(8, ADD, F, HF, F, 2, false, true, true),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8)
|
||||
return;
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
if (inst[i].opcode == BRW_OPCODE_MAC) {
|
||||
brw_MAC(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
} else {
|
||||
assert(inst[i].opcode == BRW_OPCODE_ADD);
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(inst[i].read_acc ? acc0: g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
}
|
||||
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
|
||||
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
|
||||
|
||||
if (devinfo.is_cherryview || devinfo.gen >= 9)
|
||||
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
|
||||
else
|
||||
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align1_math_strided_fp16_inputs)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned dst_stride;
|
||||
unsigned src0_stride;
|
||||
unsigned src1_stride;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, \
|
||||
dst_stride, src0_stride, src1_stride, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_HORIZONTAL_STRIDE_##dst_stride, \
|
||||
BRW_HORIZONTAL_STRIDE_##src0_stride, \
|
||||
BRW_HORIZONTAL_STRIDE_##src1_stride, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
INST(HF, HF, F, 2, 2, 1, true),
|
||||
INST(HF, F, HF, 2, 1, 2, true),
|
||||
INST(HF, F, HF, 1, 1, 2, true),
|
||||
INST(HF, F, HF, 2, 1, 1, false),
|
||||
INST(HF, HF, F, 2, 1, 1, false),
|
||||
INST(HF, HF, F, 1, 1, 1, false),
|
||||
INST(HF, HF, F, 2, 1, 1, false),
|
||||
INST( F, HF, F, 1, 1, 1, false),
|
||||
INST( F, F, HF, 1, 1, 2, true),
|
||||
INST( F, HF, HF, 1, 2, 1, false),
|
||||
INST( F, HF, HF, 1, 2, 2, true),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
/* No half-float math in gen8 */
|
||||
if (devinfo.gen < 9)
|
||||
return;
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
gen6_math(p, retype(g0, inst[i].dst_type),
|
||||
BRW_MATH_FUNCTION_POW,
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src0_stride);
|
||||
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, inst[i].src1_stride);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align1_packed_fp16_dst)
|
||||
{
|
||||
static const struct {
|
||||
unsigned exec_size;
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned dst_stride;
|
||||
unsigned dst_subnr;
|
||||
bool expected_result_bdw;
|
||||
bool expected_result_chv_skl;
|
||||
} inst[] = {
|
||||
#define INST(exec_size, dst_type, src0_type, src1_type, dst_stride, dst_subnr, \
|
||||
expected_result_bdw, expected_result_chv_skl) \
|
||||
{ \
|
||||
BRW_EXECUTE_##exec_size, \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_HORIZONTAL_STRIDE_##dst_stride, \
|
||||
dst_subnr, \
|
||||
expected_result_bdw, \
|
||||
expected_result_chv_skl \
|
||||
}
|
||||
|
||||
/* SIMD8 packed fp16 dst won't cross oword boundaries if region is
|
||||
* oword-aligned
|
||||
*/
|
||||
INST( 8, HF, HF, F, 1, 0, false, true),
|
||||
INST( 8, HF, HF, F, 1, 2, false, false),
|
||||
INST( 8, HF, HF, F, 1, 4, false, false),
|
||||
INST( 8, HF, HF, F, 1, 8, false, false),
|
||||
INST( 8, HF, HF, F, 1, 16, false, true),
|
||||
|
||||
/* SIMD16 packed fp16 always crosses oword boundaries */
|
||||
INST(16, HF, HF, F, 1, 0, false, false),
|
||||
INST(16, HF, HF, F, 1, 2, false, false),
|
||||
INST(16, HF, HF, F, 1, 4, false, false),
|
||||
INST(16, HF, HF, F, 1, 8, false, false),
|
||||
INST(16, HF, HF, F, 1, 16, false, false),
|
||||
|
||||
/* If destination is not packed (or not fp16) we can cross oword
|
||||
* boundaries
|
||||
*/
|
||||
INST( 8, HF, HF, F, 2, 0, true, true),
|
||||
INST( 8, F, HF, F, 1, 0, true, true),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8)
|
||||
return;
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr);
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
|
||||
|
||||
if (devinfo.is_cherryview || devinfo.gen >= 9)
|
||||
EXPECT_EQ(inst[i].expected_result_chv_skl, validate(p));
|
||||
else
|
||||
EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_packed_data)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned src0_vstride;
|
||||
unsigned src1_vstride;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, \
|
||||
src0_vstride, src1_vstride, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_VERTICAL_STRIDE_##src0_vstride, \
|
||||
BRW_VERTICAL_STRIDE_##src1_vstride, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST(F, F, HF, 4, 4, true),
|
||||
INST(F, F, HF, 2, 4, false),
|
||||
INST(F, F, HF, 4, 2, false),
|
||||
INST(F, F, HF, 0, 4, false),
|
||||
INST(F, F, HF, 4, 0, false),
|
||||
INST(F, HF, F, 4, 4, true),
|
||||
INST(F, HF, F, 4, 2, false),
|
||||
INST(F, HF, F, 2, 4, false),
|
||||
INST(F, HF, F, 0, 4, false),
|
||||
INST(F, HF, F, 4, 0, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_no_simd16)
|
||||
{
|
||||
static const struct {
|
||||
unsigned exec_size;
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(exec_size, dst_type, src0_type, src1_type, expected_result) \
|
||||
{ \
|
||||
BRW_EXECUTE_##exec_size, \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( 8, F, F, HF, true),
|
||||
INST( 8, F, HF, F, true),
|
||||
INST( 8, F, F, HF, true),
|
||||
INST(16, F, F, HF, false),
|
||||
INST(16, F, HF, F, false),
|
||||
INST(16, F, F, HF, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_no_acc_read)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
bool read_acc;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, read_acc, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
read_acc, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( F, F, HF, false, true),
|
||||
INST( F, F, HF, true, false),
|
||||
INST( F, HF, F, false, true),
|
||||
INST( F, HF, F, true, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
if (devinfo.gen < 8 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
brw_ADD(p, retype(g0, inst[i].dst_type),
|
||||
retype(inst[i].read_acc ? acc0 : g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, mixed_float_align16_math_packed_format)
|
||||
{
|
||||
static const struct {
|
||||
enum brw_reg_type dst_type;
|
||||
enum brw_reg_type src0_type;
|
||||
enum brw_reg_type src1_type;
|
||||
unsigned src0_vstride;
|
||||
unsigned src1_vstride;
|
||||
bool expected_result;
|
||||
} inst[] = {
|
||||
#define INST(dst_type, src0_type, src1_type, \
|
||||
src0_vstride, src1_vstride, expected_result) \
|
||||
{ \
|
||||
BRW_REGISTER_TYPE_##dst_type, \
|
||||
BRW_REGISTER_TYPE_##src0_type, \
|
||||
BRW_REGISTER_TYPE_##src1_type, \
|
||||
BRW_VERTICAL_STRIDE_##src0_vstride, \
|
||||
BRW_VERTICAL_STRIDE_##src1_vstride, \
|
||||
expected_result, \
|
||||
}
|
||||
|
||||
/* We only test with F destination because there is a restriction
|
||||
* by which F->HF conversions need to be DWord aligned but Align16 also
|
||||
* requires that destination horizontal stride is 1.
|
||||
*/
|
||||
INST( F, HF, F, 4, 0, false),
|
||||
INST( F, HF, HF, 4, 4, true),
|
||||
INST( F, F, HF, 4, 0, false),
|
||||
INST( F, F, HF, 2, 4, false),
|
||||
INST( F, F, HF, 4, 2, false),
|
||||
INST( F, HF, HF, 0, 4, false),
|
||||
|
||||
#undef INST
|
||||
};
|
||||
|
||||
/* Align16 Math for mixed float mode is not supported in gen8 */
|
||||
if (devinfo.gen < 9 || devinfo.gen >= 11)
|
||||
return;
|
||||
|
||||
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
||||
|
||||
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
|
||||
gen6_math(p, retype(g0, inst[i].dst_type),
|
||||
BRW_MATH_FUNCTION_POW,
|
||||
retype(g0, inst[i].src0_type),
|
||||
retype(g0, inst[i].src1_type));
|
||||
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, inst[i].src0_vstride);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, inst[i].src1_vstride);
|
||||
|
||||
EXPECT_EQ(inst[i].expected_result, validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, vector_immediate_destination_alignment)
|
||||
{
|
||||
static const struct {
|
||||
|
||||
Reference in New Issue
Block a user