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intel/fs: fix SHADER_OPCODE_CLUSTER_BROADCAST for SIMD32

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The current code can create functions with a width of 32, which is not
supported by our hardware. Add some code to simplify how we express
what we want and prevent such cases.

For some unknown reason, all the tests I could run seem to work even
with these unsupported MOVs.

Fixes: b0858c1cc6 "intel/fs: Add a couple of simple helper opcodes"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
This commit is contained in:
Paulo Zanoni
2019-09-04 15:07:20 -07:00
committed by Jason Ekstrand
parent c99df52873
commit 8e614c7a29
1 changed files with 10 additions and 1 deletions
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11
src/intel/compiler/brw_fs_generator.cpp
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@@ -2141,8 +2141,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
assert(src[2].type == BRW_REGISTER_TYPE_UD);
const unsigned component = src[1].ud;
const unsigned cluster_size = src[2].ud;
unsigned vstride = cluster_size;
unsigned width = cluster_size;
/* The maximum exec_size is 32, but the maximum width is only 16. */
if (inst->exec_size == width) {
vstride = 0;
width = 1;
}
struct brw_reg strided = stride(suboffset(src[0], component),
cluster_size, cluster_size, 0);
vstride, width, 0);
if (type_sz(src[0].type) > 4 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
/* IVB has an issue (which we found empirically) where it reads