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nir/opt_varyings: make top-level compaction code for TES, TCS, GS separate

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Add a separate "if" block for each and use a helper for repeated code.
There will be more code added here that keeping TES, TCS, and GS compaction
code unified would be a mess.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32424>
This commit is contained in:
Marek Olšák
2024-11-20 02:42:18 -05:00
committed by Marge Bot
parent d20e07dbad
commit 8e39e8ed4d
1 changed files with 68 additions and 46 deletions
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70
src/compiler/nir/nir_opt_varyings.c
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@@ -4553,6 +4553,26 @@ vs_tcs_tes_gs_assign_slots(struct linkage_info *linkage,
} }
} }
static void
vs_tcs_tes_gs_assign_slots_2sets(struct linkage_info *linkage,
BITSET_WORD *input32_mask,
BITSET_WORD *input16_mask,
unsigned *slot_index,
unsigned *patch_slot_index,
nir_opt_varyings_progress *progress)
{
/* Compact 32-bit inputs, followed by 16-bit inputs allowing them to
* share vec4 slots with 32-bit inputs.
*/
vs_tcs_tes_gs_assign_slots(linkage, input32_mask, slot_index,
patch_slot_index, 2, progress);
vs_tcs_tes_gs_assign_slots(linkage, input16_mask, slot_index,
patch_slot_index, 1, progress);
assert(*slot_index <= VARYING_SLOT_MAX * 8);
assert(!patch_slot_index || *patch_slot_index <= VARYING_SLOT_TESS_MAX * 8);
}
/** /**
* Compaction means scalarizing and then packing scalar components into full * Compaction means scalarizing and then packing scalar components into full
* vec4s, so that we minimize the number of unused components in vec4 slots. * vec4s, so that we minimize the number of unused components in vec4 slots.
@@ -4734,8 +4754,10 @@ compact_varyings(struct linkage_info *linkage,
NUM_SCALAR_SLOTS, false, true, color_channel_rotate, NUM_SCALAR_SLOTS, false, true, color_channel_rotate,
progress); progress);
} }
} else { return;
/* The consumer is a TCS, TES, or GS. }
/* If we get here, the consumer can only be TCS, TES, or GS.
* *
* "use_pos" says whether the driver prefers that compaction with non-FS * "use_pos" says whether the driver prefers that compaction with non-FS
* consumers puts varyings into POS first before using any VARn. * consumers puts varyings into POS first before using any VARn.
@@ -4744,7 +4766,6 @@ compact_varyings(struct linkage_info *linkage,
nir_io_dont_use_pos_for_non_fs_varyings); nir_io_dont_use_pos_for_non_fs_varyings);
unsigned slot_index = (use_pos ? VARYING_SLOT_POS unsigned slot_index = (use_pos ? VARYING_SLOT_POS
: VARYING_SLOT_VAR0) * 8; : VARYING_SLOT_VAR0) * 8;
unsigned patch_slot_index = VARYING_SLOT_PATCH0 * 8;
if (linkage->consumer_stage == MESA_SHADER_TESS_CTRL) { if (linkage->consumer_stage == MESA_SHADER_TESS_CTRL) {
/* Make tcs_cross_invoc*_mask bits disjoint with flat*_mask bits /* Make tcs_cross_invoc*_mask bits disjoint with flat*_mask bits
@@ -4756,36 +4777,37 @@ compact_varyings(struct linkage_info *linkage,
BITSET_ANDNOT(linkage->flat16_mask, linkage->flat16_mask, BITSET_ANDNOT(linkage->flat16_mask, linkage->flat16_mask,
linkage->tcs_cross_invoc16_mask); linkage->tcs_cross_invoc16_mask);
/* Compact 32-bit inputs and 16-bit inputs separately. */ /* Put cross-invocation-accessed TCS inputs first. */
vs_tcs_tes_gs_assign_slots(linkage, linkage->tcs_cross_invoc32_mask, vs_tcs_tes_gs_assign_slots_2sets(linkage, linkage->tcs_cross_invoc32_mask,
&slot_index, &patch_slot_index, 2, progress); linkage->tcs_cross_invoc16_mask,
vs_tcs_tes_gs_assign_slots(linkage, linkage->tcs_cross_invoc16_mask, &slot_index, NULL, progress);
&slot_index, &patch_slot_index, 1, progress); /* Remaining TCS inputs. */
vs_tcs_tes_gs_assign_slots_2sets(linkage, linkage->flat32_mask,
linkage->flat16_mask, &slot_index,
NULL, progress);
return;
} }
/* Compact 32-bit inputs. */ if (linkage->consumer_stage == MESA_SHADER_TESS_EVAL) {
vs_tcs_tes_gs_assign_slots(linkage, linkage->flat32_mask, &slot_index, unsigned patch_slot_index = VARYING_SLOT_PATCH0 * 8;
&patch_slot_index, 2, progress);
/* Compact 16-bit inputs, allowing them to share vec4 slots with 32-bit vs_tcs_tes_gs_assign_slots_2sets(linkage, linkage->flat32_mask,
* inputs. linkage->flat16_mask, &slot_index,
*/ &patch_slot_index, progress);
vs_tcs_tes_gs_assign_slots(linkage, linkage->flat16_mask, &slot_index,
&patch_slot_index, 1, progress);
if (linkage->producer_stage == MESA_SHADER_TESS_CTRL) {
/* Put no-varying slots last. These are TCS outputs read by TCS but /* Put no-varying slots last. These are TCS outputs read by TCS but
* not TES. * not TES.
*/ */
vs_tcs_tes_gs_assign_slots(linkage, linkage->no_varying32_mask, vs_tcs_tes_gs_assign_slots_2sets(linkage, linkage->no_varying32_mask,
&slot_index, &patch_slot_index, 2, progress); linkage->no_varying16_mask, &slot_index,
vs_tcs_tes_gs_assign_slots(linkage, linkage->no_varying16_mask, &patch_slot_index, progress);
&slot_index, &patch_slot_index, 1, progress); return;
} }
assert(slot_index <= VARYING_SLOT_MAX * 8); assert(linkage->consumer_stage == MESA_SHADER_GEOMETRY);
assert(patch_slot_index <= VARYING_SLOT_TESS_MAX * 8); vs_tcs_tes_gs_assign_slots_2sets(linkage, linkage->flat32_mask,
} linkage->flat16_mask, &slot_index,
NULL, progress);
} }
/****************************************************************** /******************************************************************