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radv: initialize meta shader options earlier

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We might need this for NIR builders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15854>
This commit is contained in:
Rhys Perry
2022-03-30 11:52:58 +01:00
committed by Marge Bot
parent 53e8d6618f
commit 8e0e98a9af
22 changed files with 98 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/amd/vulkan/radv_acceleration_structure.c
View File

@@ -976,7 +976,7 @@ static nir_shader *
build_leaf_shader(struct radv_device *dev)
{
const struct glsl_type *vec3_type = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_leaf_shader");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "accel_build_leaf_shader");
b.shader->info.workgroup_size[0] = 64;
@@ -1293,7 +1293,7 @@ static nir_shader *
build_internal_shader(struct radv_device *dev)
{
const struct glsl_type *vec3_type = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_build_internal_shader");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "accel_build_internal_shader");
b.shader->info.workgroup_size[0] = 64;
@@ -1395,7 +1395,7 @@ struct copy_constants {
static nir_shader *
build_copy_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "accel_copy");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "accel_copy");
b.shader->info.workgroup_size[0] = 64;
nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);

12
src/amd/vulkan/radv_meta.c
View File

@@ -659,7 +659,8 @@ radv_device_finish_meta(struct radv_device *device)
mtx_destroy(&device->meta_state.mtx);
}
nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const char *name, ...)
nir_builder PRINTFLIKE(3, 4)
radv_meta_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...)
{
nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);
if (name) {
@@ -669,6 +670,7 @@ nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const
va_end(args);
}
b.shader->options = &dev->physical_device->nir_options[stage];
b.shader->info.workgroup_size[0] = 1;
b.shader->info.workgroup_size[1] = 1;
b.shader->info.workgroup_size[2] = 1;
@@ -710,13 +712,13 @@ radv_meta_gen_rect_vertices(nir_builder *vs_b)
/* vertex shader that generates vertices */
nir_shader *
radv_meta_build_nir_vs_generate_vertices(void)
radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_variable *v_position;
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_vs_gen_verts");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_vs_gen_verts");
nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
@@ -729,9 +731,9 @@ radv_meta_build_nir_vs_generate_vertices(void)
}
nir_shader *
radv_meta_build_nir_fs_noop(void)
radv_meta_build_nir_fs_noop(struct radv_device *dev)
{
return radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
return radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
}
void

7
src/amd/vulkan/radv_meta.h
View File

@@ -254,11 +254,12 @@ radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)
/* common nir builder helpers */
#include "nir/nir_builder.h"
nir_builder PRINTFLIKE(2, 3) radv_meta_init_shader(gl_shader_stage stage, const char *name, ...);
nir_builder PRINTFLIKE(3, 4)
radv_meta_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...);
nir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b);
nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2);
nir_shader *radv_meta_build_nir_vs_generate_vertices(void);
nir_shader *radv_meta_build_nir_fs_noop(void);
nir_shader *radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev);
nir_shader *radv_meta_build_nir_fs_noop(struct radv_device *dev);
void radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples,
nir_variable *input_img, nir_variable *color,

26
src/amd/vulkan/radv_meta_blit.c
View File

@@ -36,10 +36,10 @@ static VkResult build_pipeline(struct radv_device *device, VkImageAspectFlagBits
VkPipeline *pipeline);
static nir_shader *
build_nir_vertex_shader(void)
build_nir_vertex_shader(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_blit_vs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_blit_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -79,10 +79,10 @@ build_nir_vertex_shader(void)
}
static nir_shader *
build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
build_nir_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -126,10 +126,11 @@ build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
}
static nir_shader *
build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
build_nir_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -173,10 +174,11 @@ build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
}
static nir_shader *
build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
build_nir_copy_fragment_shader_stencil(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -669,7 +671,7 @@ build_pipeline(struct radv_device *device, VkImageAspectFlagBits aspect,
}
nir_shader *fs;
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
VkPipelineRenderingCreateInfo rendering_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
@@ -677,16 +679,16 @@ build_pipeline(struct radv_device *device, VkImageAspectFlagBits aspect,
switch (aspect) {
case VK_IMAGE_ASPECT_COLOR_BIT:
fs = build_nir_copy_fragment_shader(tex_dim);
fs = build_nir_copy_fragment_shader(device, tex_dim);
rendering_create_info.colorAttachmentCount = 1;
rendering_create_info.pColorAttachmentFormats = &format;
break;
case VK_IMAGE_ASPECT_DEPTH_BIT:
fs = build_nir_copy_fragment_shader_depth(tex_dim);
fs = build_nir_copy_fragment_shader_depth(device, tex_dim);
rendering_create_info.depthAttachmentFormat = format;
break;
case VK_IMAGE_ASPECT_STENCIL_BIT:
fs = build_nir_copy_fragment_shader_stencil(tex_dim);
fs = build_nir_copy_fragment_shader_stencil(device, tex_dim);
rendering_create_info.stencilAttachmentFormat = format;
break;
default:

16
src/amd/vulkan/radv_meta_blit2d.c
View File

@@ -386,11 +386,11 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_sur
}
static nir_shader *
build_nir_vertex_shader(void)
build_nir_vertex_shader(struct radv_device *device)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_blit2d_vs");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_VERTEX, "meta_blit2d_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -527,7 +527,7 @@ build_nir_copy_fragment_shader(struct radv_device *device, texel_fetch_build_fun
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -550,7 +550,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device, texel_fetch_bui
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -573,7 +573,7 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device, texel_fetch_b
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -653,7 +653,7 @@ blit2d_init_color_pipeline(struct radv_device *device, enum blit2d_src_type src_
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
nir_shader *fs = build_nir_copy_fragment_shader(
device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
vi_create_info = &normal_vi_create_info;
@@ -788,7 +788,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device, enum blit2d_src_type
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
nir_shader *fs = build_nir_copy_fragment_shader_depth(
device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
vi_create_info = &normal_vi_create_info;
@@ -945,7 +945,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device, enum blit2d_src_ty
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
nir_shader *fs = build_nir_copy_fragment_shader_stencil(
device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
vi_create_info = &normal_vi_create_info;

4
src/amd/vulkan/radv_meta_buffer.c
View File

@@ -7,7 +7,7 @@
static nir_shader *
build_buffer_fill_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_fill");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_fill");
b.shader->info.workgroup_size[0] = 64;
nir_ssa_def *global_id = get_global_ids(&b, 1);
@@ -29,7 +29,7 @@ build_buffer_fill_shader(struct radv_device *dev)
static nir_shader *
build_buffer_copy_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_buffer_copy");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_copy");
b.shader->info.workgroup_size[0] = 64;
nir_ssa_def *global_id = get_global_ids(&b, 1);

14
src/amd/vulkan/radv_meta_bufimage.c
View File

@@ -39,7 +39,7 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
const struct glsl_type *sampler_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b =
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
@@ -220,7 +220,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b =
radv_meta_init_shader(MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
@@ -398,7 +398,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
const struct glsl_type *buf_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
@@ -550,7 +550,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples)
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *buf_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE,
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE,
is_3d ? "meta_itoi_cs_3d-%d" : "meta_itoi_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -749,7 +749,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
const struct glsl_type *type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "input_img");
@@ -908,7 +908,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(
MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
dev, MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1064,7 +1064,7 @@ static nir_shader *
build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

33
src/amd/vulkan/radv_meta_clear.c
View File

@@ -32,11 +32,12 @@
enum { DEPTH_CLEAR_SLOW, DEPTH_CLEAR_FAST };
static void
build_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs, uint32_t frag_output)
build_color_shaders(struct radv_device *dev, struct nir_shader **out_vs, struct nir_shader **out_fs,
uint32_t frag_output)
{
nir_builder vs_b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_clear_color_vs");
nir_builder vs_b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_clear_color_vs");
nir_builder fs_b =
radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
const struct glsl_type *position_type = glsl_vec4_type();
const struct glsl_type *color_type = glsl_vec4_type();
@@ -182,7 +183,7 @@ create_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t fra
return VK_SUCCESS;
}
build_color_shaders(&vs_nir, &fs_nir, frag_output);
build_color_shaders(device, &vs_nir, &fs_nir, frag_output);
const VkPipelineVertexInputStateCreateInfo vi_state = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
@@ -384,13 +385,14 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl
}
static void
build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs, bool unrestricted)
build_depthstencil_shader(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, bool unrestricted)
{
nir_builder vs_b = radv_meta_init_shader(
MESA_SHADER_VERTEX,
dev, MESA_SHADER_VERTEX,
unrestricted ? "meta_clear_depthstencil_unrestricted_vs" : "meta_clear_depthstencil_vs");
nir_builder fs_b = radv_meta_init_shader(
MESA_SHADER_FRAGMENT,
dev, MESA_SHADER_FRAGMENT,
unrestricted ? "meta_clear_depthstencil_unrestricted_fs" : "meta_clear_depthstencil_fs");
const struct glsl_type *position_out_type = glsl_vec4_type();
@@ -445,7 +447,7 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe
return VK_SUCCESS;
}
build_depthstencil_shader(&vs_nir, &fs_nir, unrestricted);
build_depthstencil_shader(device, &vs_nir, &fs_nir, unrestricted);
const VkPipelineVertexInputStateCreateInfo vi_state = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
@@ -903,9 +905,9 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
}
static nir_shader *
build_clear_htile_mask_shader()
build_clear_htile_mask_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
b.shader->info.workgroup_size[0] = 64;
nir_ssa_def *global_id = get_global_ids(&b, 1);
@@ -933,7 +935,7 @@ init_meta_clear_htile_mask_state(struct radv_device *device)
{
struct radv_meta_state *state = &device->meta_state;
VkResult result;
nir_shader *cs = build_clear_htile_mask_shader();
nir_shader *cs = build_clear_htile_mask_shader(device);
VkDescriptorSetLayoutCreateInfo ds_layout_info = {
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
@@ -1000,13 +1002,14 @@ fail:
* For MSAA images, clearing the first sample should be enough as long as CMASK is also cleared.
*/
static nir_shader *
build_clear_dcc_comp_to_single_shader(bool is_msaa)
build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa)
{
enum glsl_sampler_dim dim = is_msaa ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, true, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
is_msaa ? "multisampled" : "singlesampled");
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
is_msaa ? "multisampled" : "singlesampled");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1049,7 +1052,7 @@ create_dcc_comp_to_single_pipeline(struct radv_device *device, bool is_msaa, VkP
{
struct radv_meta_state *state = &device->meta_state;
VkResult result;
nir_shader *cs = build_clear_dcc_comp_to_single_shader(is_msaa);
nir_shader *cs = build_clear_dcc_comp_to_single_shader(device, is_msaa);
VkPipelineShaderStageCreateInfo shader_stage = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,

2
src/amd/vulkan/radv_meta_copy_vrs_htile.c
View File

@@ -44,7 +44,7 @@ radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
static nir_shader *
build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
{
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

2
src/amd/vulkan/radv_meta_dcc_retile.c
View File

@@ -32,7 +32,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur
{
enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "dcc_retile_compute");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

6
src/amd/vulkan/radv_meta_decompress.c
View File

@@ -38,7 +38,7 @@ build_expand_depth_stencil_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
b.shader->info.workgroup_size[0] = 8;
@@ -176,8 +176,8 @@ create_pipeline(struct radv_device *device, uint32_t samples, VkPipelineLayout l
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices();
nir_shader *fs_module = radv_meta_build_nir_fs_noop();
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
if (!vs_module || !fs_module) {
/* XXX: Need more accurate error */

3
src/amd/vulkan/radv_meta_etc_decode.c
View File

@@ -172,10 +172,9 @@ build_shader(struct radv_device *dev)
glsl_image_type(GLSL_SAMPLER_DIM_2D, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type_3d =
glsl_image_type(GLSL_SAMPLER_DIM_3D, false, GLSL_TYPE_FLOAT);
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_decode_etc");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_decode_etc");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
b.shader->info.workgroup_size[2] = 1;
nir_variable *input_img_2d =
nir_variable_create(b.shader, nir_var_uniform, sampler_type_2d, "s_tex_2d");

6
src/amd/vulkan/radv_meta_fast_clear.c
View File

@@ -39,7 +39,7 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "dcc_decompress_compute");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_decompress_compute");
/* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
b.shader->info.workgroup_size[0] = 16;
@@ -168,7 +168,7 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
nir_shader *fs_module = radv_meta_build_nir_fs_noop();
nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
if (!fs_module) {
/* XXX: Need more accurate error */
@@ -421,7 +421,7 @@ radv_device_init_meta_fast_clear_flush_state_internal(struct radv_device *device
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices();
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
if (!vs_module) {
/* XXX: Need more accurate error */
res = VK_ERROR_OUT_OF_HOST_MEMORY;

3
src/amd/vulkan/radv_meta_fmask_copy.c
View File

@@ -29,7 +29,8 @@ build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

3
src/amd/vulkan/radv_meta_fmask_expand.c
View File

@@ -33,7 +33,8 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples)
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, true, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
nir_builder b =
radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;

10
src/amd/vulkan/radv_meta_resolve.c
View File

@@ -32,12 +32,12 @@
/* emit 0, 0, 0, 1 */
static nir_shader *
build_nir_fs(void)
build_nir_fs(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_variable *f_color; /* vec4, fragment output color */
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs");
f_color = nir_variable_create(b.shader, nir_var_shader_out, vec4, "f_color");
f_color->data.location = FRAG_RESULT_DATA0;
@@ -53,7 +53,7 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkFormat
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
nir_shader *fs_module = build_nir_fs();
nir_shader *fs_module = build_nir_fs(device);
if (!fs_module) {
/* XXX: Need more accurate error */
result = VK_ERROR_OUT_OF_HOST_MEMORY;
@@ -206,7 +206,7 @@ radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand)
VkResult res = VK_SUCCESS;
struct radv_meta_state *state = &device->meta_state;
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices();
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
if (!vs_module) {
/* XXX: Need more accurate error */
res = VK_ERROR_OUT_OF_HOST_MEMORY;
@@ -345,7 +345,7 @@ build_resolve_pipeline(struct radv_device *device, unsigned fs_key)
return result;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices();
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
VkShaderModule vs_module_h = vk_shader_module_handle_from_nir(vs_module);
result = create_pipeline(device, vs_module_h, radv_fs_key_format_exemplars[fs_key],

4
src/amd/vulkan/radv_meta_resolve_cs.c
View File

@@ -64,7 +64,7 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
is_integer ? "int" : (is_srgb ? "srgb" : "float"));
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -134,7 +134,7 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, true, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
b.shader->info.workgroup_size[0] = 8;

14
src/amd/vulkan/radv_meta_resolve_fs.c
View File

@@ -31,10 +31,10 @@
#include "vk_format.h"
static nir_shader *
build_nir_vertex_shader(void)
build_nir_vertex_shader(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(MESA_SHADER_VERTEX, "meta_resolve_vs");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_resolve_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -52,8 +52,8 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s", samples,
is_integer ? "int" : "float");
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s",
samples, is_integer ? "int" : "float");
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;
@@ -147,7 +147,7 @@ create_resolve_pipeline(struct radv_device *device, int samples_log2, VkFormat f
is_integer = true;
nir_shader *fs = build_resolve_fragment_shader(device, is_integer, samples);
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -269,7 +269,7 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
index == DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
@@ -401,7 +401,7 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples_lo
uint32_t samples = 1 << samples_log2;
nir_shader *fs =
build_depth_stencil_resolve_fragment_shader(device, samples, index, resolve_mode);
nir_shader *vs = build_nir_vertex_shader();
nir_shader *vs = build_nir_vertex_shader(device);
VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -4236,7 +4236,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
}
if (!stages[MESA_SHADER_FRAGMENT].entrypoint && !stages[MESA_SHADER_COMPUTE].entrypoint) {
nir_builder fs_b = radv_meta_init_shader(MESA_SHADER_FRAGMENT, "noop_fs");
nir_builder fs_b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "noop_fs");
stages[MESA_SHADER_FRAGMENT] = (struct radv_pipeline_stage) {
.stage = MESA_SHADER_FRAGMENT,

7
src/amd/vulkan/radv_pipeline_rt.c
View File

@@ -23,6 +23,7 @@
#include "radv_acceleration_structure.h"
#include "radv_debug.h"
#include "radv_meta.h"
#include "radv_private.h"
#include "radv_rt_common.h"
#include "radv_shader.h"
@@ -1690,12 +1691,10 @@ create_rt_shader(struct radv_device *device, const VkRayTracingPipelineCreateInf
struct radv_pipeline_key key;
memset(&key, 0, sizeof(key));
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "rt_combined");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "rt_combined");
b.shader->info.internal = false;
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = device->physical_device->rt_wave_size == 64 ? 8 : 4;
b.shader->info.workgroup_size[2] = 1;
struct rt_variables vars = create_rt_variables(b.shader, stack_sizes);
load_sbt_entry(&b, &vars, nir_imm_int(&b, 0), SBT_RAYGEN, 0);
@@ -1745,8 +1744,6 @@ create_rt_shader(struct radv_device *device, const VkRayTracingPipelineCreateInf
const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->pStages[shader_id];
nir_shader *nir_stage = parse_rt_stage(device, stage);
b.shader->options = nir_stage->options;
uint32_t num_resume_shaders = 0;
nir_shader **resume_shaders = NULL;
nir_lower_shader_calls(nir_stage, nir_address_format_32bit_offset, 16, &resume_shaders,

8
src/amd/vulkan/radv_query.c
View File

@@ -116,7 +116,7 @@ build_occlusion_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "occlusion_query");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "occlusion_query");
b.shader->info.workgroup_size[0] = 64;
nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
@@ -251,7 +251,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "pipeline_statistics_query");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "pipeline_statistics_query");
b.shader->info.workgroup_size[0] = 64;
nir_variable *output_offset =
@@ -386,7 +386,7 @@ build_tfb_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "tfb_query");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "tfb_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */
@@ -507,7 +507,7 @@ build_timestamp_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "timestamp_query");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "timestamp_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */

3
src/amd/vulkan/radv_shader.c
View File

@@ -574,7 +574,6 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipelin
* and just use the NIR shader. We don't want to alter meta and RT
* shaders IR directly, so clone it first. */
nir = nir_shader_clone(NULL, stage->internal_nir);
nir->options = &device->physical_device->nir_options[stage->stage];
nir_validate_shader(nir, "in internal shader");
assert(exec_list_length(&nir->functions) == 1);
@@ -2072,7 +2071,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
if (!trap)
return NULL;
nir_builder b = radv_meta_init_shader(MESA_SHADER_COMPUTE, "meta_trap_handler");
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_trap_handler");
options.wgp_mode = radv_should_use_wgp_mode(device, MESA_SHADER_COMPUTE, &info);
info.wave_size = 64;