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freedreno/a5xx+a6xx: use sysmem path for nondraw batches

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For prologue's in the nondraw path, we need a "gmem" rb that we can emit
the IB to the prologue before the main part of the batch.  This has the
side benefit of cleaning up a bunch of duplicate setup code in a5xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6475>
This commit is contained in:
Rob Clark
2020-08-26 14:57:52 -07:00
committed by Marge Bot
parent 21b90708a4
commit 8d9ab0a33b
8 changed files with 26 additions and 71 deletions
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20
src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
View File

@@ -153,23 +153,6 @@ can_do_blit(const struct pipe_blit_info *info)
static void
emit_setup(struct fd_ringbuffer *ring)
{
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, LRZ_FLUSH);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
OUT_RING(ring, 0x00000008);
@@ -459,9 +442,6 @@ fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
fd5_emit_restore(batch, batch->draw);
fd5_emit_lrz_flush(batch->draw);
emit_setup(batch->draw);
if ((info->src.resource->target == PIPE_BUFFER) &&

31
src/gallium/drivers/freedreno/a5xx/fd5_compute.c
View File

@@ -149,35 +149,6 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
fd5_emit_shader(ring, v);
}
static void
emit_setup(struct fd_context *ctx)
{
struct fd_ringbuffer *ring = ctx->batch->draw;
fd5_emit_restore(ctx->batch, ring);
fd5_emit_lrz_flush(ring);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
fd_wfi(ctx->batch, ring);
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
}
static void
fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
{
@@ -187,8 +158,6 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned nglobal = 0;
emit_setup(ctx);
v = ir3_shader_variant(so->shader, key, false, &ctx->debug);
if (!v)
return;

17
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
View File

@@ -693,7 +693,6 @@ fd5_emit_tile_fini(struct fd_batch *batch)
static void
fd5_emit_sysmem_prep(struct fd_batch *batch)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
fd5_emit_restore(batch, ring);
@@ -720,6 +719,17 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
A5XX_RB_CNTL_HEIGHT(0) |
A5XX_RB_CNTL_BYPASS);
/* remaining setup below here does not apply to blit/compute: */
if (batch->nondraw)
return;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
@@ -739,11 +749,6 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
OUT_RING(ring, 0x1);
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
A5XX_RB_CNTL_HEIGHT(0) |
A5XX_RB_CNTL_BYPASS);
patch_draws(batch, IGNORE_VISIBILITY);
emit_zs(ring, pfb->zsbuf, NULL);

3
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View File

@@ -698,9 +698,6 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
fd6_emit_restore(batch, batch->draw);
fd6_emit_lrz_flush(batch->draw);
fd_screen_lock(ctx->screen);
fd_batch_resource_read(batch, fd_resource(info->src.resource));

2
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View File

@@ -140,8 +140,6 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned nglobal = 0;
fd6_emit_restore(ctx->batch, ring);
v = ir3_shader_variant(so->shader, key, false, &ctx->debug);
if (!v)
return;

7
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View File

@@ -1360,7 +1360,6 @@ setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
static void
fd6_emit_sysmem_prep(struct fd_batch *batch)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
fd6_emit_restore(batch, ring);
@@ -1372,6 +1371,12 @@ fd6_emit_sysmem_prep(struct fd_batch *batch)
fd_log(batch, "END PROLOGUE");
}
/* remaining setup below here does not apply to blit/compute: */
if (batch->nondraw)
return;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (pfb->width > 0 && pfb->height > 0)
set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
else

15
src/gallium/drivers/freedreno/freedreno_batch.c
View File

@@ -64,7 +64,8 @@ batch_init(struct fd_batch *batch)
batch->submit = fd_submit_new(ctx->pipe);
if (batch->nondraw) {
batch->draw = alloc_ring(batch, 0x100000, FD_RINGBUFFER_PRIMARY);
batch->gmem = alloc_ring(batch, 0x1000, FD_RINGBUFFER_PRIMARY);
batch->draw = alloc_ring(batch, 0x100000, 0);
} else {
batch->gmem = alloc_ring(batch, 0x100000, FD_RINGBUFFER_PRIMARY);
batch->draw = alloc_ring(batch, 0x100000, 0);
@@ -155,13 +156,11 @@ batch_fini(struct fd_batch *batch)
fd_fence_ref(&batch->fence, NULL);
fd_ringbuffer_del(batch->draw);
if (!batch->nondraw) {
if (batch->binning)
fd_ringbuffer_del(batch->binning);
fd_ringbuffer_del(batch->gmem);
} else {
debug_assert(!batch->binning);
debug_assert(!batch->gmem);
fd_ringbuffer_del(batch->gmem);
if (batch->binning) {
fd_ringbuffer_del(batch->binning);
batch->binning = NULL;
}
if (batch->prologue) {

2
src/gallium/drivers/freedreno/freedreno_gmem.c
View File

@@ -603,6 +603,7 @@ render_tiles(struct fd_batch *batch, struct fd_gmem_stateobj *gmem)
} else {
ctx->screen->emit_ib(batch->gmem, batch->draw);
}
fd_log(batch, "TILE[%d]: END DRAW IB", i);
fd_reset_wfi(batch);
@@ -711,6 +712,7 @@ fd_gmem_render_tiles(struct fd_batch *batch)
if (batch->nondraw) {
DBG("%p: rendering non-draw", batch);
render_sysmem(batch);
ctx->stats.batch_nondraw++;
} else if (sysmem) {
fd_log(batch, "%p: rendering sysmem %ux%u (%s/%s), num_draws=%u",