etnaviv: use feature bit for one const src per instuction limitation
Support for multiple constant sources per instruction is not a HALTI5 capability, there is a separate feature bit to signal the availability of this shader core enhancement. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
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@@ -65,7 +65,7 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst)
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if (inst->imm && inst->src[2].use)
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if (inst->imm && inst->src[2].use)
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return 1;
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return 1;
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if (!inst->halti5 && !check_uniforms(inst))
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if (!inst->no_oneconst_limit && !check_uniforms(inst))
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BUG("error: generating instruction that accesses two different uniforms");
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BUG("error: generating instruction that accesses two different uniforms");
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assert(!(inst->opcode&~0x7f));
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assert(!(inst->opcode&~0x7f));
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@@ -97,7 +97,7 @@ struct etna_inst {
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unsigned sel_bit0:1; /* select low half mediump */
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unsigned sel_bit0:1; /* select low half mediump */
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unsigned sel_bit1:1; /* select high half mediump */
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unsigned sel_bit1:1; /* select high half mediump */
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unsigned dst_full:1; /* write to highp register */
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unsigned dst_full:1; /* write to highp register */
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unsigned halti5:1; /* allow multiple different uniform sources */
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unsigned no_oneconst_limit:1; /* allow multiple different uniform sources */
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struct etna_inst_dst dst; /* destination operand */
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struct etna_inst_dst dst; /* destination operand */
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struct etna_inst_tex tex; /* texture operand */
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struct etna_inst_tex tex; /* texture operand */
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struct etna_inst_src src[ETNA_NUM_SRC]; /* source operand */
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struct etna_inst_src src[ETNA_NUM_SRC]; /* source operand */
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@@ -732,7 +732,7 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
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* -insert movs (nir_lower_vec_to_movs equivalent)
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* -insert movs (nir_lower_vec_to_movs equivalent)
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* for non-vecN instructions:
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* for non-vecN instructions:
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* -try to merge constants as single constant
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* -try to merge constants as single constant
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* -insert movs for multiple constants (pre-HALTI5)
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* -insert movs for multiple constants if required
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*/
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*/
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static void
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static void
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lower_alu(struct etna_compile *c, nir_alu_instr *alu)
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lower_alu(struct etna_compile *c, nir_alu_instr *alu)
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@@ -749,8 +749,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
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case nir_op_vec4:
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case nir_op_vec4:
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break;
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break;
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default:
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default:
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/* pre-GC7000L can only have 1 uniform src per instruction */
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if (c->specs->has_no_oneconst_limit)
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if (c->specs->halti >= 5)
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return;
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return;
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nir_const_value value[4] = {};
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nir_const_value value[4] = {};
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@@ -1195,7 +1194,7 @@ etna_compile_shader(struct etna_shader_variant *v)
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if (inst->opcode == INST_OPCODE_BRANCH)
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if (inst->opcode == INST_OPCODE_BRANCH)
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inst->imm = block_ptr[inst->imm];
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inst->imm = block_ptr[inst->imm];
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inst->halti5 = specs->halti >= 5;
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inst->no_oneconst_limit = specs->has_no_oneconst_limit;
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etna_assemble(&code[i * 4], inst);
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etna_assemble(&code[i * 4], inst);
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}
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}
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@@ -77,6 +77,8 @@ struct etna_specs {
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unsigned has_new_transcendentals : 1;
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unsigned has_new_transcendentals : 1;
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/* has the new dp2/dpX_norm instructions, among others */
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/* has the new dp2/dpX_norm instructions, among others */
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unsigned has_halti2_instructions : 1;
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unsigned has_halti2_instructions : 1;
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/* has no limit on the number of constant sources per instruction */
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unsigned has_no_oneconst_limit : 1;
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/* has V4_COMPRESSION */
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/* has V4_COMPRESSION */
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unsigned v4_compression : 1;
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unsigned v4_compression : 1;
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/* supports single-buffer rendering with multiple pixel pipes */
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/* supports single-buffer rendering with multiple pixel pipes */
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@@ -837,6 +837,8 @@ etna_get_specs(struct etna_screen *screen)
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VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
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VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
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screen->specs.has_halti2_instructions =
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screen->specs.has_halti2_instructions =
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VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
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VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
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screen->specs.has_no_oneconst_limit =
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VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT);
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screen->specs.v4_compression =
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screen->specs.v4_compression =
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VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
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VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
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screen->specs.seamless_cube_map =
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screen->specs.seamless_cube_map =
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