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radv/gfx10: move emitting VGT_PRIMITIVEID_EN into the NGG path

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And do not emit VGT_GS_MODE which is unnecessary on GFX10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Samuel Pitoiset
2019-07-18 10:14:07 +02:00
parent 8315dbe419
commit 8c692ff512
1 changed files with 11 additions and 6 deletions
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17
src/amd/vulkan/radv_pipeline.c
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@@ -3274,18 +3274,15 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
unsigned vgt_primitiveid_en = 0; unsigned vgt_primitiveid_en = 0;
uint32_t vgt_gs_mode = 0; uint32_t vgt_gs_mode = 0;
if (radv_pipeline_has_ngg(pipeline))
return;
if (radv_pipeline_has_gs(pipeline)) { if (radv_pipeline_has_gs(pipeline)) {
const struct radv_shader_variant *gs = const struct radv_shader_variant *gs =
pipeline->shaders[MESA_SHADER_GEOMETRY]; pipeline->shaders[MESA_SHADER_GEOMETRY];
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class); pipeline->device->physical_device->rad_info.chip_class);
} else if (radv_pipeline_has_ngg(pipeline)) {
bool enable_prim_id =
outinfo->export_prim_id || vs->info.info.uses_prim_id;
vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) |
S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id);
} else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) { } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A); vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1); vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
@@ -3425,6 +3422,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
gl_shader_stage es_type = gl_shader_stage es_type =
radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
struct radv_shader_variant *es =
es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8); radeon_emit(cs, va >> 8);
@@ -3441,6 +3440,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
bool misc_vec_ena = outinfo->writes_pointsize || bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer || outinfo->writes_layer ||
outinfo->writes_viewport_index; outinfo->writes_viewport_index;
bool es_enable_prim_id = outinfo->export_prim_id ||
(es && es->info.info.uses_prim_id);
bool break_wave_at_eoi = false; bool break_wave_at_eoi = false;
unsigned nparams; unsigned nparams;
@@ -3479,6 +3480,10 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
cull_dist_mask << 8 | cull_dist_mask << 8 |
clip_dist_mask); clip_dist_mask);
radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 && bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 && pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
es_type == MESA_SHADER_TESS_EVAL; es_type == MESA_SHADER_TESS_EVAL;