anv: change the way we clear pending query bits

Instead of having genX(emit_apply_pipe_flushes) doing the clearing,
ask genX(emit_apply_pipe_flushes) for the emitted bits and do the
clearing using a helper.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23675>

src/intel/vulkan/anv_cmd_buffer.c

@@ -298,6 +298,29 @@ anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer)
    anv_genX(devinfo, cmd_emit_conditional_render_predicate)(cmd_buffer);
 }
 
+void
+anv_cmd_buffer_update_pending_query_bits(struct anv_cmd_buffer *cmd_buffer,
+                                         enum anv_pipe_bits flushed_bits)
+{
+   if (flushed_bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
+      cmd_buffer->state.pending_query_bits &= ~ANV_QUERY_WRITES_RT_FLUSH;
+
+   if (flushed_bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)
+      cmd_buffer->state.pending_query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH;
+
+   if ((flushed_bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT) &&
+       (flushed_bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) &&
+       (flushed_bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT))
+      cmd_buffer->state.pending_query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH;
+
+   /* Once RT/TILE have been flushed, we can consider the CS_STALL flush */
+   if ((cmd_buffer->state.pending_query_bits & (ANV_QUERY_WRITES_TILE_FLUSH |
+                                                ANV_QUERY_WRITES_RT_FLUSH |
+                                                ANV_QUERY_WRITES_DATA_FLUSH)) == 0 &&
+       (flushed_bits & (ANV_PIPE_END_OF_PIPE_SYNC_BIT | ANV_PIPE_CS_STALL_BIT)))
+      cmd_buffer->state.pending_query_bits &= ~ANV_QUERY_WRITES_CS_STALL;
+}
+
 static bool
 mem_update(void *dst, const void *src, size_t size)
 {

src/intel/vulkan/anv_genX.h

@@ -104,7 +104,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
                               struct anv_device *device,
                               uint32_t current_pipeline,
                               enum anv_pipe_bits bits,
-                              enum anv_query_bits *query_bits);
+                              enum anv_pipe_bits *emitted_flush_bits);
 
 void genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
                                struct anv_device *device,

src/intel/vulkan/anv_private.h

@@ -3144,6 +3144,10 @@ void
 anv_cmd_buffer_clflush(struct anv_cmd_buffer **cmd_buffers,
                        uint32_t num_cmd_buffers);
 
+void
+anv_cmd_buffer_update_pending_query_bits(struct anv_cmd_buffer *cmd_buffer,
+                                         enum anv_pipe_bits flushed_bits);
+
 /**
  * A allocation tied to a command buffer.
  *

src/intel/vulkan/genX_cmd_buffer.c

@@ -1392,7 +1392,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
                               struct anv_device *device,
                               uint32_t current_pipeline,
                               enum anv_pipe_bits bits,
-                              enum anv_query_bits *query_bits)
+                              enum anv_pipe_bits *emitted_flush_bits)
 {
 #if GFX_VER >= 12
    /* From the TGL PRM, Volume 2a, "PIPE_CONTROL":
@@ -1601,28 +1601,11 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
       genX(batch_emit_pipe_control_write)(batch, device->info, sync_op, addr,
                                           0, flush_bits);
 
-      /* Based on emitted flushes, clear the associated buffer write tracking
+      /* If the caller wants to know what flushes have been emitted,
-       * bits of buffer writes.
+       * provide the bits based off the PIPE_CONTROL programmed bits.
        */
-      if (query_bits != NULL) {
+      if (emitted_flush_bits != NULL)
-         if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
+         *emitted_flush_bits = flush_bits;
-            *query_bits &= ~ANV_QUERY_WRITES_RT_FLUSH;
-
-         if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)
-            *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH;
-
-         if ((bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT) &&
-             (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) &&
-             (bits & ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT))
-            *query_bits &= ~ANV_QUERY_WRITES_TILE_FLUSH;
-
-         /* Once RT/TILE have been flushed, we can consider the CS_STALL flush */
-         if ((*query_bits & (ANV_QUERY_WRITES_TILE_FLUSH |
-                             ANV_QUERY_WRITES_RT_FLUSH |
-                             ANV_QUERY_WRITES_DATA_FLUSH)) == 0 &&
-             (bits & (ANV_PIPE_END_OF_PIPE_SYNC_BIT | ANV_PIPE_CS_STALL_BIT)))
-            *query_bits &= ~ANV_QUERY_WRITES_CS_STALL;
-      }
 
       bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS |
                 ANV_PIPE_END_OF_PIPE_SYNC_BIT);
@@ -1751,12 +1734,15 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
              sizeof(cmd_buffer->state.gfx.ib_dirty_range));
    }
 
+
+   enum anv_pipe_bits emitted_bits = 0;
    cmd_buffer->state.pending_pipe_bits =
       genX(emit_apply_pipe_flushes)(&cmd_buffer->batch,
                                     cmd_buffer->device,
                                     cmd_buffer->state.current_pipeline,
                                     bits,
-                                    &cmd_buffer->state.pending_query_bits);
+                                    &emitted_bits);
+   anv_cmd_buffer_update_pending_query_bits(cmd_buffer, emitted_bits);
 
 #if INTEL_NEEDS_WA_1508744258
    if (rhwo_opt_change) {

src/intel/vulkan/genX_cmd_draw_generated_indirect.h

@@ -369,7 +369,7 @@ genX(cmd_buffer_flush_generated_draws)(struct anv_cmd_buffer *cmd_buffer)
 #endif
                                  ANV_PIPE_DATA_CACHE_FLUSH_BIT |
                                  ANV_PIPE_CS_STALL_BIT,
-                                 NULL /* query_bits */);
+                                 NULL /* emitted_bits */);
 
 #if GFX_VER >= 12
    anv_batch_emit(batch, GENX(MI_ARB_CHECK), arb) {

src/intel/vulkan/genX_simple_shader.h

@@ -505,8 +505,10 @@ genX(emit_simple_shader_dispatch)(struct anv_simple_shader *state,
        *     these scoreboard related states, a MEDIA_STATE_FLUSH is
        *     sufficient."
        */
+      enum anv_pipe_bits emitted_bits = 0;
       genX(emit_apply_pipe_flushes)(batch, device, GPGPU, ANV_PIPE_CS_STALL_BIT,
-                                    &state->cmd_buffer->state.pending_query_bits);
+                                    &emitted_bits);
+      anv_cmd_buffer_update_pending_query_bits(state->cmd_buffer, emitted_bits);
 
       anv_batch_emit(batch, GENX(MEDIA_VFE_STATE), vfe) {
          vfe.StackSize              = 0;