intel/fs: Add support for subgroup quad operations

NIR has code to lower these away for us but we can do significantly
better in many cases with register regioning and SIMD4x2.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

src/intel/compiler/brw_shader.cpp

@@ -334,6 +334,8 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
       return "shuffle";
    case SHADER_OPCODE_SEL_EXEC:
       return "sel_exec";
+   case SHADER_OPCODE_QUAD_SWIZZLE:
+      return "quad_swizzle";
    case SHADER_OPCODE_CLUSTER_BROADCAST:
       return "cluster_broadcast";