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radv: reformat according to its .clang-format

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Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23253>
This commit is contained in:
Eric Engestrom
2023-05-26 12:56:20 +01:00
committed by Marge Bot
parent 1725d9aa67
commit 8b319c6db8
92 changed files with 7729 additions and 11330 deletions
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129
src/amd/vulkan/radv_pipeline.c
View File

@@ -71,13 +71,11 @@ bool
radv_pipeline_capture_shader_stats(const struct radv_device *device, VkPipelineCreateFlags flags)
{
return (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
device->keep_shader_info;
(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) || device->keep_shader_info;
}
void
radv_pipeline_init(struct radv_device *device, struct radv_pipeline *pipeline,
enum radv_pipeline_type type)
radv_pipeline_init(struct radv_device *device, struct radv_pipeline *pipeline, enum radv_pipeline_type type)
{
vk_object_base_init(&device->vk, &pipeline->base, VK_OBJECT_TYPE_PIPELINE);
@@ -114,8 +112,7 @@ radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline
}
VKAPI_ATTR void VKAPI_CALL
radv_DestroyPipeline(VkDevice _device, VkPipeline _pipeline,
const VkAllocationCallbacks *pAllocator)
radv_DestroyPipeline(VkDevice _device, VkPipeline _pipeline, const VkAllocationCallbacks *pAllocator)
{
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
@@ -137,12 +134,10 @@ radv_pipeline_init_scratch(const struct radv_device *device, struct radv_pipelin
if (pipeline->shaders[i] && (pipeline->shaders[i]->config.scratch_bytes_per_wave || is_rt)) {
unsigned max_stage_waves = device->scratch_waves;
scratch_bytes_per_wave =
MAX2(scratch_bytes_per_wave, pipeline->shaders[i]->config.scratch_bytes_per_wave);
scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave, pipeline->shaders[i]->config.scratch_bytes_per_wave);
max_stage_waves =
MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_cu *
radv_get_max_waves(device, pipeline->shaders[i], i));
max_stage_waves = MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_cu *
radv_get_max_waves(device, pipeline->shaders[i], i));
max_waves = MAX2(max_waves, max_stage_waves);
}
}
@@ -162,11 +157,10 @@ radv_generate_pipeline_key(const struct radv_device *device, const struct radv_p
if (flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
key.optimisations_disabled = 1;
key.disable_aniso_single_level = device->instance->disable_aniso_single_level &&
device->physical_device->rad_info.gfx_level < GFX8;
key.disable_aniso_single_level =
device->instance->disable_aniso_single_level && device->physical_device->rad_info.gfx_level < GFX8;
key.image_2d_view_of_3d =
device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9;
key.image_2d_view_of_3d = device->image_2d_view_of_3d && device->physical_device->rad_info.gfx_level == GFX9;
key.tex_non_uniform = device->instance->tex_non_uniform;
@@ -210,11 +204,10 @@ radv_get_hash_flags(const struct radv_device *device, bool stats)
}
void
radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo,
struct radv_pipeline_stage *out_stage, gl_shader_stage stage)
radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, struct radv_pipeline_stage *out_stage,
gl_shader_stage stage)
{
const VkShaderModuleCreateInfo *minfo =
vk_find_struct_const(sinfo->pNext, SHADER_MODULE_CREATE_INFO);
const VkShaderModuleCreateInfo *minfo = vk_find_struct_const(sinfo->pNext, SHADER_MODULE_CREATE_INFO);
const VkPipelineShaderStageModuleIdentifierCreateInfoEXT *iinfo =
vk_find_struct_const(sinfo->pNext, PIPELINE_SHADER_STAGE_MODULE_IDENTIFIER_CREATE_INFO_EXT);
@@ -251,8 +244,7 @@ ycbcr_conversion_lookup(const void *data, uint32_t set, uint32_t binding, uint32
const struct radv_pipeline_layout *layout = data;
const struct radv_descriptor_set_layout *set_layout = layout->set[set].layout;
const struct vk_ycbcr_conversion_state *ycbcr_samplers =
radv_immutable_ycbcr_samplers(set_layout, binding);
const struct vk_ycbcr_conversion_state *ycbcr_samplers = radv_immutable_ycbcr_samplers(set_layout, binding);
if (!ycbcr_samplers)
return NULL;
@@ -261,9 +253,8 @@ ycbcr_conversion_lookup(const void *data, uint32_t set, uint32_t binding, uint32
}
bool
radv_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size,
unsigned num_components, nir_intrinsic_instr *low,
nir_intrinsic_instr *high, void *data)
radv_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components,
nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data)
{
if (num_components > 4)
return false;
@@ -300,8 +291,7 @@ radv_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned
FALLTHROUGH;
case nir_intrinsic_load_shared:
case nir_intrinsic_store_shared:
if (bit_size * num_components ==
96) { /* 96 bit loads require 128 bit alignment and are split otherwise */
if (bit_size * num_components == 96) { /* 96 bit loads require 128 bit alignment and are split otherwise */
return align % 16 == 0;
} else if (bit_size == 16 && (align % 4)) {
/* AMD hardware can't do 2-byte aligned f16vec2 loads, but they are useful for ALU
@@ -359,8 +349,7 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
case nir_op_isign:
case nir_op_uadd_sat:
case nir_op_usub_sat:
return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32
: 0;
return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32 : 0;
case nir_op_iadd_sat:
case nir_op_isub_sat:
return bit_size == 8 || !nir_dest_is_divergent(alu->dest.dest) ? 32 : 0;
@@ -383,8 +372,7 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
case nir_op_ine:
case nir_op_ult:
case nir_op_uge:
return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32
: 0;
return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32 : 0;
default:
return 0;
}
@@ -470,8 +458,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
}
enum nir_lower_non_uniform_access_type lower_non_uniform_access_types =
nir_lower_non_uniform_ubo_access | nir_lower_non_uniform_ssbo_access |
nir_lower_non_uniform_texture_access | nir_lower_non_uniform_image_access;
nir_lower_non_uniform_ubo_access | nir_lower_non_uniform_ssbo_access | nir_lower_non_uniform_texture_access |
nir_lower_non_uniform_image_access;
/* In practice, most shaders do not have non-uniform-qualified
* accesses (see
@@ -495,8 +483,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
NIR_PASS(_, stage->nir, nir_lower_memory_model);
nir_load_store_vectorize_options vectorize_opts = {
.modes = nir_var_mem_ssbo | nir_var_mem_ubo | nir_var_mem_push_const | nir_var_mem_shared |
nir_var_mem_global,
.modes = nir_var_mem_ssbo | nir_var_mem_ubo | nir_var_mem_push_const | nir_var_mem_shared | nir_var_mem_global,
.callback = radv_mem_vectorize_callback,
.robust_modes = 0,
/* On GFX6, read2/write2 is out-of-bounds if the offset register is negative, even if
@@ -514,8 +501,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
NIR_PASS(progress, stage->nir, nir_opt_load_store_vectorize, &vectorize_opts);
if (progress) {
NIR_PASS(_, stage->nir, nir_copy_prop);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores,
!device->instance->disable_shrink_image_store);
NIR_PASS(_, stage->nir, nir_opt_shrink_stores, !device->instance->disable_shrink_image_store);
/* Gather info again, to update whether 8/16-bit are used. */
nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir));
@@ -551,8 +537,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
if (stage->nir->info.uses_resource_info_query)
NIR_PASS(_, stage->nir, ac_nir_lower_resinfo, gfx_level);
NIR_PASS_V(stage->nir, radv_nir_apply_pipeline_layout, device, pipeline_layout, &stage->info,
&stage->args);
NIR_PASS_V(stage->nir, radv_nir_apply_pipeline_layout, device, pipeline_layout, &stage->info, &stage->args);
if (!pipeline_key->optimisations_disabled) {
NIR_PASS(_, stage->nir, nir_opt_shrink_vectors);
@@ -570,16 +555,14 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
sink_opts |= nir_move_load_input;
NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts);
NIR_PASS(_, stage->nir, nir_opt_move,
nir_move_load_input | nir_move_const_undef | nir_move_copies);
NIR_PASS(_, stage->nir, nir_opt_move, nir_move_load_input | nir_move_const_undef | nir_move_copies);
}
/* Lower VS inputs. We need to do this after nir_opt_sink, because
* load_input can be reordered, but buffer loads can't.
*/
if (stage->stage == MESA_SHADER_VERTEX) {
NIR_PASS(_, stage->nir, radv_nir_lower_vs_inputs, stage, pipeline_key,
&device->physical_device->rad_info);
NIR_PASS(_, stage->nir, radv_nir_lower_vs_inputs, stage, pipeline_key, &device->physical_device->rad_info);
}
/* Lower I/O intrinsics to memory instructions. */
@@ -592,8 +575,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
NIR_PASS_V(stage->nir, ac_nir_lower_legacy_vs, gfx_level,
stage->info.outinfo.clip_dist_mask | stage->info.outinfo.cull_dist_mask,
stage->info.outinfo.vs_output_param_offset, stage->info.outinfo.param_exports,
stage->info.outinfo.export_prim_id, false, false,
stage->info.force_vrs_per_vertex);
stage->info.outinfo.export_prim_id, false, false, stage->info.force_vrs_per_vertex);
} else {
ac_nir_gs_output_info gs_out_info = {
@@ -614,11 +596,9 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
* present.
*/
.alpha_to_coverage_via_mrtz = stage->info.ps.writes_mrt0_alpha,
.dual_src_blend_swizzle =
pipeline_key->ps.epilog.mrt0_is_dual_src && gfx_level >= GFX11,
.dual_src_blend_swizzle = pipeline_key->ps.epilog.mrt0_is_dual_src && gfx_level >= GFX11,
/* Need to filter out unwritten color slots. */
.spi_shader_col_format =
pipeline_key->ps.epilog.spi_shader_col_format & stage->info.ps.colors_written,
.spi_shader_col_format = pipeline_key->ps.epilog.spi_shader_col_format & stage->info.ps.colors_written,
.color_is_int8 = pipeline_key->ps.epilog.color_is_int8,
.color_is_int10 = pipeline_key->ps.epilog.color_is_int10,
.alpha_func = COMPARE_FUNC_ALWAYS,
@@ -648,9 +628,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
NIR_PASS(_, stage->nir, ac_nir_lower_global_access);
NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, &stage->info, &stage->args, pipeline_key,
device->physical_device->rad_info.address32_hi);
radv_optimize_nir_algebraic(stage->nir, io_to_mem || lowered_ngg ||
stage->stage == MESA_SHADER_COMPUTE ||
stage->stage == MESA_SHADER_TASK);
radv_optimize_nir_algebraic(
stage->nir, io_to_mem || lowered_ngg || stage->stage == MESA_SHADER_COMPUTE || stage->stage == MESA_SHADER_TASK);
if (stage->nir->info.bit_sizes_int & (8 | 16)) {
if (gfx_level >= GFX8) {
@@ -665,16 +644,13 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
if (gfx_level >= GFX8)
NIR_PASS(_, stage->nir, nir_opt_remove_phis); /* cleanup LCSSA phis */
}
if (((stage->nir->info.bit_sizes_int | stage->nir->info.bit_sizes_float) & 16) &&
gfx_level >= GFX9) {
if (((stage->nir->info.bit_sizes_int | stage->nir->info.bit_sizes_float) & 16) && gfx_level >= GFX9) {
bool separate_g16 = gfx_level >= GFX10;
struct nir_fold_tex_srcs_options fold_srcs_options[] = {
{
.sampler_dims =
~(BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE) | BITFIELD_BIT(GLSL_SAMPLER_DIM_BUF)),
.src_types = (1 << nir_tex_src_coord) | (1 << nir_tex_src_lod) |
(1 << nir_tex_src_bias) | (1 << nir_tex_src_min_lod) |
(1 << nir_tex_src_ms_index) |
.sampler_dims = ~(BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE) | BITFIELD_BIT(GLSL_SAMPLER_DIM_BUF)),
.src_types = (1 << nir_tex_src_coord) | (1 << nir_tex_src_lod) | (1 << nir_tex_src_bias) |
(1 << nir_tex_src_min_lod) | (1 << nir_tex_src_ms_index) |
(separate_g16 ? 0 : (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy)),
},
{
@@ -708,8 +684,8 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layo
sink_opts |= nir_move_comparisons | nir_move_load_ubo | nir_move_load_ssbo;
NIR_PASS(_, stage->nir, nir_opt_sink, sink_opts);
nir_move_options move_opts = nir_move_const_undef | nir_move_load_ubo | nir_move_load_input |
nir_move_comparisons | nir_move_copies;
nir_move_options move_opts =
nir_move_const_undef | nir_move_load_ubo | nir_move_load_input | nir_move_comparisons | nir_move_copies;
NIR_PASS(_, stage->nir, nir_opt_move, move_opts);
}
}
@@ -725,8 +701,7 @@ radv_get_executable_count(struct radv_pipeline *pipeline)
if (!pipeline->shaders[i])
continue;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
if (i == MESA_SHADER_GEOMETRY && !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
ret += 2u;
} else {
ret += 1u;
@@ -736,8 +711,7 @@ radv_get_executable_count(struct radv_pipeline *pipeline)
}
static struct radv_shader *
radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index,
gl_shader_stage *stage)
radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
{
if (pipeline->type == RADV_PIPELINE_RAY_TRACING) {
*stage = MESA_SHADER_INTERSECTION;
@@ -754,8 +728,7 @@ radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index,
--index;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
if (i == MESA_SHADER_GEOMETRY && !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
if (!index) {
*stage = i;
return pipeline->gs_copy_shader;
@@ -781,8 +754,7 @@ desc_copy(char *desc, const char *src)
VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPipelineExecutablePropertiesKHR(VkDevice _device, const VkPipelineInfoKHR *pPipelineInfo,
uint32_t *pExecutableCount,
VkPipelineExecutablePropertiesKHR *pProperties)
uint32_t *pExecutableCount, VkPipelineExecutablePropertiesKHR *pProperties)
{
RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
const uint32_t total_count = radv_get_executable_count(pipeline);
@@ -879,8 +851,7 @@ radv_GetPipelineExecutablePropertiesKHR(VkDevice _device, const VkPipelineInfoKH
desc_copy(pProperties[executable_idx].description, description);
++executable_idx;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
if (i == MESA_SHADER_GEOMETRY && !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
assert(pipeline->gs_copy_shader);
if (executable_idx >= count)
break;
@@ -901,10 +872,8 @@ radv_GetPipelineExecutablePropertiesKHR(VkDevice _device, const VkPipelineInfoKH
}
VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPipelineExecutableStatisticsKHR(VkDevice _device,
const VkPipelineExecutableInfoKHR *pExecutableInfo,
uint32_t *pStatisticCount,
VkPipelineExecutableStatisticKHR *pStatistics)
radv_GetPipelineExecutableStatisticsKHR(VkDevice _device, const VkPipelineExecutableInfoKHR *pExecutableInfo,
uint32_t *pStatisticCount, VkPipelineExecutableStatisticKHR *pStatistics)
{
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
@@ -915,7 +884,8 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device,
const struct radv_physical_device *pdevice = device->physical_device;
unsigned lds_increment = pdevice->rad_info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT
? 1024 : pdevice->rad_info.lds_encode_granularity;
? 1024
: pdevice->rad_info.lds_encode_granularity;
unsigned max_waves = radv_get_max_waves(device, shader, stage);
VkPipelineExecutableStatisticKHR *s = pStatistics;
@@ -1039,8 +1009,7 @@ radv_copy_representation(void *data, size_t *data_size, const char *src)
VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPipelineExecutableInternalRepresentationsKHR(
VkDevice _device, const VkPipelineExecutableInfoKHR *pExecutableInfo,
uint32_t *pInternalRepresentationCount,
VkDevice _device, const VkPipelineExecutableInfoKHR *pExecutableInfo, uint32_t *pInternalRepresentationCount,
VkPipelineExecutableInternalRepresentationKHR *pInternalRepresentations)
{
RADV_FROM_HANDLE(radv_device, device, _device);
@@ -1123,12 +1092,10 @@ radv_copy_shader_stage_create_info(struct radv_device *device, uint32_t stageCou
for (uint32_t i = 0; i < stageCount; i++) {
RADV_FROM_HANDLE(vk_shader_module, module, new_stages[i].module);
const VkShaderModuleCreateInfo *minfo =
vk_find_struct_const(pStages[i].pNext, SHADER_MODULE_CREATE_INFO);
const VkShaderModuleCreateInfo *minfo = vk_find_struct_const(pStages[i].pNext, SHADER_MODULE_CREATE_INFO);
if (module) {
struct vk_shader_module *new_module =
ralloc_size(mem_ctx, sizeof(struct vk_shader_module) + module->size);
struct vk_shader_module *new_module = ralloc_size(mem_ctx, sizeof(struct vk_shader_module) + module->size);
if (!new_module)
return NULL;