OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler: Enable lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts for pre-Gfx7

Browse Source 
GLSL IR opcodes generated for bitfieldExtract and bitfieldInsert are
lowered by lower_instructions.  4dff3ff005 ("nir/opt_algebraic:
Optimize open coded bfm.") adds an optimization that can rematerialize
nir_op_bfm that was prevented by the GLSL IR lowering.

It appears that every piece of hardware, except older Intel GPUS, that
has real integers (i.e., lower_bitops is not set) also sets
lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 4dff3ff005 ("nir/opt_algebraic: Optimize open coded bfm.")
Closes: #7874
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20323>
This commit is contained in:
Ian Romanick
2022-12-13 09:43:39 -08:00
parent 13f7ef5e0c
commit 8ab7ec0129
1 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/intel/compiler/brw_compiler.c
View File

@@ -34,8 +34,6 @@
.lower_scmp = true, \
.lower_flrp16 = true, \
.lower_fmod = true, \
.lower_bitfield_extract = true, \
.lower_bitfield_insert = true, \
.lower_uadd_carry = true, \
.lower_usub_borrow = true, \
.lower_flrp64 = true, \
@@ -183,6 +181,11 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
nir_options->lower_fpow = devinfo->ver >= 12;
nir_options->lower_bitfield_extract = devinfo->ver >= 7;
nir_options->lower_bitfield_extract_to_shifts = devinfo->ver < 7;
nir_options->lower_bitfield_insert = devinfo->ver >= 7;
nir_options->lower_bitfield_insert_to_shifts = devinfo->ver < 7;
nir_options->lower_rotate = devinfo->ver < 11;
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->has_iadd3 = devinfo->verx10 >= 125;