From 8ab7ec01290232121d92c58d565e2f131f238911 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 13 Dec 2022 09:43:39 -0800 Subject: [PATCH] intel/compiler: Enable lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts for pre-Gfx7 GLSL IR opcodes generated for bitfieldExtract and bitfieldInsert are lowered by lower_instructions. 4dff3ff005b ("nir/opt_algebraic: Optimize open coded bfm.") adds an optimization that can rematerialize nir_op_bfm that was prevented by the GLSL IR lowering. It appears that every piece of hardware, except older Intel GPUS, that has real integers (i.e., lower_bitops is not set) also sets lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts. Reviewed-by: Emma Anholt Reviewed-by: Matt Turner Fixes: 4dff3ff005b ("nir/opt_algebraic: Optimize open coded bfm.") Closes: #7874 Part-of: --- src/intel/compiler/brw_compiler.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index e7fc9053729..1cfc23842ea 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -34,8 +34,6 @@ .lower_scmp = true, \ .lower_flrp16 = true, \ .lower_fmod = true, \ - .lower_bitfield_extract = true, \ - .lower_bitfield_insert = true, \ .lower_uadd_carry = true, \ .lower_usub_borrow = true, \ .lower_flrp64 = true, \ @@ -183,6 +181,11 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11; nir_options->lower_fpow = devinfo->ver >= 12; + nir_options->lower_bitfield_extract = devinfo->ver >= 7; + nir_options->lower_bitfield_extract_to_shifts = devinfo->ver < 7; + nir_options->lower_bitfield_insert = devinfo->ver >= 7; + nir_options->lower_bitfield_insert_to_shifts = devinfo->ver < 7; + nir_options->lower_rotate = devinfo->ver < 11; nir_options->lower_bitfield_reverse = devinfo->ver < 7; nir_options->has_iadd3 = devinfo->verx10 >= 125;